Comments (5)
Looking at the checks, it seems like rvfi_intr is ignored.
Yeah, that's because rocket doesn't really set it yet either and PicoRV32 is only verified in non-interrupt mode (because it's using a non-standard interrupt mechanism that pre-dates the priv spec).
This should be added to rvfi_pc_fwd_check
and rvfi_pc_bwd_check
. (Both checks could need some love in general.) I will fix this soon-ish.
My implementation sets rvfi_pc_wdata to the start of the trap handler for each instruction that causes a fault
That also works.
I tried keeping those values for rvfi_rs1_addr and rvfi_rs2_addr, but I failed checks for addi, lui, and other similar instructions
That's a bug in rvfi_insn_check.sv
. What you are doing should work (as long as the value on rvfi_rs1_rdata
/rvfi_rs2_rdata
correctly represents the machine state). I will fix this some time this week.
from riscv-formal.
Thanks for the quick reply. As I said, I have all the checks passing without any changes to riscv-formal, so it's not urgent.
from riscv-formal.
The rs1/rs2
issue should be fixed now. (The intr
issue is still open.)
from riscv-formal.
I have also encountered this, with the pc_fwd
check. I update pc_wdata
for instructions which retire as an interrupt is asserted, as suggested above. The solver immediately finds a loophole in this: it asserts an interrupt in a pipeline bubble between two instructions, which it creates by starving instruction fetch briefly.
The earlier instruction has already retired, so its pc_wdata
points to the sequentially-next instruction. However, the next instruction to actually retire is the first instruction of the interrupt handler, which is nonsequential with the previous instruction. This fails the check.
I am trying to come up with a workaround for this, but all I can think of at the moment is "retiring" a dummy nop
in the interrupted bubble to link up the pre-interrupt pc_wdata
with the in-interrupt pc_rdata
, which is a bit of a hack.
I am also playing with hacking my local copy of pc_fwd_ch0
to not check pc_rdata
on cycles where rvfi_intr
is asserted, but then I need additional properties to check that e.g. rvfi_intr
is not just tied high.
As an aside, moving to the latest version of riscv-formal (I was around 40 commits behind) has found a lot of nasty bugs in my processor, so thank you for all the hard work there :)
from riscv-formal.
Had posted a message here about rs2_addr error getting flagged for ADDI but was wrong. I thought it was complaining about ADDI rs2_addr but it was actually rs1_addr. Nothing to see here :)
from riscv-formal.
Related Issues (20)
- Adding support for a newRISC-V processor to riscv-formal HOT 4
- Failed Checks in picorv32 Verification Following Quickstart Guide HOT 3
- Misaligned JAL(R) RD register writeback expectations HOT 4
- JAL handling procedure HOT 1
- Value of rs1 during CSR*I instructions HOT 2
- OOPS forget i said anything
- Incorrect width of insn_funct6 in I-type (shift variation) instruction format?
- Debug modelling
- "ERROR: syntax error, unexpected TOK_RAND" in quick start guide HOT 2
- Instruction checks: non-universal assertions should be generated based on instruction type
- How to set values in the genchecks.cfg file?
- Support for Zce?
- When is rvfi_halt supposed to be used?
- rvfi_reg_check is possibly broken (picorv32 also fails the assertion) HOT 3
- Can WARL read-only be handled in csrw_check?
- are rvfi_valid and rvfi_trap mutually exclusive.
- Some confusion about skip option
- Is this repo no longer active?
- syntax error in quickstart HOT 1
- RV32I and RV64I
Recommend Projects
-
React
A declarative, efficient, and flexible JavaScript library for building user interfaces.
-
Vue.js
🖖 Vue.js is a progressive, incrementally-adoptable JavaScript framework for building UI on the web.
-
Typescript
TypeScript is a superset of JavaScript that compiles to clean JavaScript output.
-
TensorFlow
An Open Source Machine Learning Framework for Everyone
-
Django
The Web framework for perfectionists with deadlines.
-
Laravel
A PHP framework for web artisans
-
D3
Bring data to life with SVG, Canvas and HTML. 📊📈🎉
-
Recommend Topics
-
javascript
JavaScript (JS) is a lightweight interpreted programming language with first-class functions.
-
web
Some thing interesting about web. New door for the world.
-
server
A server is a program made to process requests and deliver data to clients.
-
Machine learning
Machine learning is a way of modeling and interpreting data that allows a piece of software to respond intelligently.
-
Visualization
Some thing interesting about visualization, use data art
-
Game
Some thing interesting about game, make everyone happy.
Recommend Org
-
Facebook
We are working to build community through open source technology. NB: members must have two-factor auth.
-
Microsoft
Open source projects and samples from Microsoft.
-
Google
Google ❤️ Open Source for everyone.
-
Alibaba
Alibaba Open Source for everyone
-
D3
Data-Driven Documents codes.
-
Tencent
China tencent open source team.
from riscv-formal.