Syntacore custom modification problems about scr1

[achuykov-sc]

@GARIIKK,

Could you please check the linker script for your application (CoreMark)?
The default entry point is 0x200. So, if you had changed the reset vector address, you should change linker script according to your changes.

Best regards,
Alexander

[GARIIKK]

Hello @achuykov-sc ,
Sorry for delayed answer. I have found the problem. It is closely connected with my SyntaCore2Wishbone bridge. I reread your documentation on AHB and AXI bus. But I still cant understand how I should do this communication properly. I did some changes with delaying(pipelining) of some request/response signals to/from Wishbone BUS. After this modification Core starts execute the instruction, writes and reads from Data memory. But still does it incorrectly(compare to another RISC-V core which 100% works correctly with the same soft, linker script, etc.). Could you please describe this SyntaCore2BUS communication in more details?
Regards,
Ilya

[achuykov-sc]

Hi Ilya,

Could you please more details? You had mentioned: "But still does it incorrectly". What exactly is incorrect?
Please attach waves and logs.

Best regards,
Alexander