Comments (2)
Fixed it locally, will push soon.. (it's in the read_GPR_EX function in
instructions.h).
On 05/10/2013 12:28 AM, jeuneS2 wrote:
The test case vliw_test/add (and possibly other test cases) show
inconsistent forwarding in the simulator. In the first cycle, r1 is
assigned 2 in pipeline 0 and 5 in pipeline 1. r2-r7 are assigned r1+r1
in the subsequent cycles. The result is that r1=5 (result from pipeline
1), r2=r3=4 (apparently forwarded from pipeline 0), and r4=r5=r6=r7=10
(forwarded from pipeline 1 or the register file). This should be fixed
such that the value in the register and the forwarded values are consistent.—
Reply to this email directly or view it on GitHub
#4.
Stefan Hepp E: [email protected]
Vienna University of Technology W: www.complang.tuwien.ac.at/hepp
Institute of Computer Languages T: +43-1-58801-185181
Austria, 1040 Wien, Argentinierstr.8
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Pushed it, r2-r7 = 10 now in the vliw add.s test.
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