Quartus 20.1 failing to flash Patmos onto DE2-115 about patmos

[epsilon-0311]

I built now patmos using Quartus 19.1 and 20.1 and attached the log here.
What catches my eye is that the used resources increased from 18897 to 118824, but the RAM Segments were reduced from 322 to 190. The higher amount of resources is probably the reason why the fitting and routing process tackes 17 minutes instead of a few seconds.

Would be interesting why quartus uses logic cells instead of RAM cells

Synthesis log output of v19.1:

...
[0m[0;32mInfo (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 745 ps
[0m[0;32mInfo (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:07
[0m[0;32mInfo (16010): Generating hard_block partition "hard_block:auto_generated_inst"
[0m[0;32m    Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL
[0m[0;32mInfo (21057): Implemented 19285 device resources after synthesis - the final resource count might be different
[0m[0;32m    Info (21058): Implemented 6 input pins
[0m[0;32m    Info (21059): Implemented 35 output pins
[0m[0;32m    Info (21060): Implemented 16 bidirectional pins
[0m[0;32m    Info (21061): Implemented 18897 logic cells
[0m[0;32m    Info (21064): Implemented 322 RAM segments
[0m[0;32m    Info (21065): Implemented 1 PLLs
[0m[0;32m    Info (21062): Implemented 8 DSP elements
[0m[0;32mInfo: Quartus Prime Analysis & Synthesis was successful. 0 errors, 33 warnings
[0m[0;32m    Info: Peak virtual memory: 1337 megabytes
[0m[0;32m    Info: Processing ended: Wed Sep 15 08:32:55 2021
[0m[0;32m    Info: Elapsed time: 00:01:04
[0m[0;32m    Info: Total CPU time (on all processors): 00:01:13
...

Synthesis log output of v20.1:

...
[0m[0;32mInfo (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 330 ps
[0m[0;32mInfo (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:27
[0m[0;32mInfo (16010): Generating hard_block partition "hard_block:auto_generated_inst"
[0m[0;32m    Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL
[0m[0;32mInfo (21057): Implemented 119080 device resources after synthesis - the final resource count might be different
[0m[0;32m    Info (21058): Implemented 6 input pins
[0m[0;32m    Info (21059): Implemented 35 output pins
[0m[0;32m    Info (21060): Implemented 16 bidirectional pins
[0m[0;32m    Info (21061): Implemented 118824 logic cells
[0m[0;32m    Info (21064): Implemented 190 RAM segments
[0m[0;32m    Info (21065): Implemented 1 PLLs
[0m[0;32m    Info (21062): Implemented 8 DSP elements
[0m[0;32mInfo: Quartus Prime Analysis & Synthesis was successful. 0 errors, 25 warnings
[0m[0;32m    Info: Peak virtual memory: 1181 megabytes
[0m[0;32m    Info: Processing ended: Wed Sep 15 09:49:49 2021
[0m[0;32m    Info: Elapsed time: 00:02:48
[0m[0;32m    Info: Total CPU time (on all processors): 00:02:57
...

build_log_quartus_20.1.log
build_log_quartus_19.1.log

[epsilon-0311]

I posted a question on Reddit, according to this the reason for the high usage of logic cells instead of using RAM Blocks is that there is asynchronous access to the RAM Block. Quartus 19.1 infered pass through logic where v20.1 uninferes RAM Blocks and uses logic cells.

It looks like there is an issue with the generated verilog code from chisel.

Synthesis log output of v19.1:

...
[0m[0;36mWarning (276020): Inferred RAM node "Patmos:comp|PatmosCore:cores_0|DataCache:dcache|DirectMappedCache:dm|MemBlock_4:tagMem|mem_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
[0m[0;36mWarning (276020): Inferred RAM node "Patmos:comp|PatmosCore:cores_0|DataCache:dcache|DirectMappedCache:dm|MemBlock_5:MemBlock_3|mem_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
[0m[0;36mWarning (276020): Inferred RAM node "Patmos:comp|PatmosCore:cores_0|DataCache:dcache|StackCache:sc|MemBlock_9:MemBlock_3|mem_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
[0m[0;36mWarning (276020): Inferred RAM node "Patmos:comp|PatmosCore:cores_0|Exceptions:exc|vec_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
[0m[0;36mWarning (276020): Inferred RAM node "Patmos:comp|PatmosCore:cores_0|DataCache:dcache|DirectMappedCache:dm|MemBlock_5:MemBlock_1|mem_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
[0m[0;36mWarning (276020): Inferred RAM node "Patmos:comp|PatmosCore:cores_0|DataCache:dcache|StackCache:sc|MemBlock_9:MemBlock_1|mem_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
[0m[0;36mWarning (276020): Inferred RAM node "Patmos:comp|PatmosCore:cores_0|DataCache:dcache|DirectMappedCache:dm|MemBlock_5:MemBlock_2|mem_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
[0m[0;36mWarning (276020): Inferred RAM node "Patmos:comp|PatmosCore:cores_0|DataCache:dcache|StackCache:sc|MemBlock_9:MemBlock_2|mem_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
[0m[0;36mWarning (276020): Inferred RAM node "Patmos:comp|PatmosCore:cores_0|DataCache:dcache|DirectMappedCache:dm|MemBlock_5:MemBlock|mem_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
[0m[0;36mWarning (276020): Inferred RAM node "Patmos:comp|PatmosCore:cores_0|DataCache:dcache|StackCache:sc|MemBlock_9:MemBlock|mem_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
[0m[0;36mWarning (276020): Inferred RAM node "Patmos:comp|UartCmp:UartCmp|Uart:uart|QueueCompatibility:txQueue|ram_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
[0m[0;36mWarning (276020): Inferred RAM node "Patmos:comp|PatmosCore:cores_0|Exceptions:exc|vecDup_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
[0m[0;36mWarning (276020): Inferred RAM node "Patmos:comp|PatmosCore:cores_0|Fetch:fetch|MemBlock_2:MemBlock_1|mem_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
[0m[0;36mWarning (276020): Inferred RAM node "Patmos:comp|PatmosCore:cores_0|Fetch:fetch|MemBlock_2:MemBlock|mem_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
[0m[0;36mWarning (276020): Inferred RAM node "Patmos:comp|PatmosCore:cores_0|MCache:icache|MCacheMem:mem|MemBlock:mcacheEven|mem_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
[0m[0;36mWarning (276020): Inferred RAM node "Patmos:comp|PatmosCore:cores_0|MCache:icache|MCacheMem:mem|MemBlock:mcacheOdd|mem_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
[0m[0;36mWarning (276020): Inferred RAM node "Patmos:comp|UartCmp:UartCmp|Uart:uart|QueueCompatibility:rxQueue|ram_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.

...

Synthesis log output of v20.1:

...
[[0m[0;36mWarning (276020): Inferred RAM node "Patmos:comp|PatmosCore:cores_0|DataCache:dcache|StackCache:sc|MemBlock_9:MemBlock_3|mem_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
[0m[0;36mWarning (276020): Inferred RAM node "Patmos:comp|PatmosCore:cores_0|DataCache:dcache|StackCache:sc|MemBlock_9:MemBlock_1|mem_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
[0m[0;36mWarning (276020): Inferred RAM node "Patmos:comp|PatmosCore:cores_0|DataCache:dcache|StackCache:sc|MemBlock_9:MemBlock_2|mem_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
[0m[0;36mWarning (276020): Inferred RAM node "Patmos:comp|PatmosCore:cores_0|DataCache:dcache|StackCache:sc|MemBlock_9:MemBlock|mem_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
[0m[0;36mWarning (276020): Inferred RAM node "Patmos:comp|PatmosCore:cores_0|Exceptions:exc|vecDup_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
[0m[0;36mWarning (276020): Inferred RAM node "Patmos:comp|PatmosCore:cores_0|Fetch:fetch|MemBlock_2:MemBlock_1|mem_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
[0m[0;36mWarning (276020): Inferred RAM node "Patmos:comp|PatmosCore:cores_0|Fetch:fetch|MemBlock_2:MemBlock|mem_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
[0m[0;36mWarning (276020): Inferred RAM node "Patmos:comp|PatmosCore:cores_0|MCache:icache|MCacheMem:mem|MemBlock:mcacheEven|mem_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
[0m[0;36mWarning (276020): Inferred RAM node "Patmos:comp|PatmosCore:cores_0|MCache:icache|MCacheMem:mem|MemBlock:mcacheOdd|mem_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
[0m[0;32mInfo (276014): Found 12 instances of uninferred RAM logic
[0m[0;32m    Info (276007): RAM logic "Patmos:comp|PatmosCore:cores_0|DataCache:dcache|DirectMappedCache:dm|MemBlock_4:tagMem|mem" is uninferred due to asynchronous read logic File: /opt/t-crest/patmos/hardware/build/Patmos.v Line: 6420
[0m[0;32m    Info (276007): RAM logic "Patmos:comp|PatmosCore:cores_0|DataCache:dcache|DirectMappedCache:dm|MemBlock_5:MemBlock_3|mem" is uninferred due to asynchronous read logic File: /opt/t-crest/patmos/hardware/build/Patmos.v Line: 6523
[0m[0;32m    Info (276007): RAM logic "Patmos:comp|PatmosCore:cores_0|Exceptions:exc|vec" is uninferred due to asynchronous read logic File: /opt/t-crest/patmos/hardware/build/Patmos.v Line: 5454
[0m[0;32m    Info (276007): RAM logic "Patmos:comp|Spm:Spm|MemBlock_9:MemBlock_3|mem" is uninferred due to asynchronous read logic File: /opt/t-crest/patmos/hardware/build/Patmos.v Line: 12292
[0m[0;32m    Info (276007): RAM logic "Patmos:comp|PatmosCore:cores_0|DataCache:dcache|DirectMappedCache:dm|MemBlock_5:MemBlock_1|mem" is uninferred due to asynchronous read logic File: /opt/t-crest/patmos/hardware/build/Patmos.v Line: 6523
[0m[0;32m    Info (276007): RAM logic "Patmos:comp|Spm:Spm|MemBlock_9:MemBlock_1|mem" is uninferred due to asynchronous read logic File: /opt/t-crest/patmos/hardware/build/Patmos.v Line: 12292
[0m[0;32m    Info (276007): RAM logic "Patmos:comp|PatmosCore:cores_0|DataCache:dcache|DirectMappedCache:dm|MemBlock_5:MemBlock_2|mem" is uninferred due to asynchronous read logic File: /opt/t-crest/patmos/hardware/build/Patmos.v Line: 6523
[0m[0;32m    Info (276007): RAM logic "Patmos:comp|Spm:Spm|MemBlock_9:MemBlock_2|mem" is uninferred due to asynchronous read logic File: /opt/t-crest/patmos/hardware/build/Patmos.v Line: 12292
[0m[0;32m    Info (276007): RAM logic "Patmos:comp|PatmosCore:cores_0|DataCache:dcache|DirectMappedCache:dm|MemBlock_5:MemBlock|mem" is uninferred due to asynchronous read logic File: /opt/t-crest/patmos/hardware/build/Patmos.v Line: 6523
[0m[0;32m    Info (276007): RAM logic "Patmos:comp|Spm:Spm|MemBlock_9:MemBlock|mem" is uninferred due to asynchronous read logic File: /opt/t-crest/patmos/hardware/build/Patmos.v Line: 12292
[0m[0;32m    Info (276007): RAM logic "Patmos:comp|UartCmp:UartCmp|Uart:uart|QueueCompatibility:txQueue|ram" is uninferred due to asynchronous read logic File: /opt/t-crest/patmos/hardware/build/Patmos.v Line: 14823
[0m[0;32m    Info (276007): RAM logic "Patmos:comp|UartCmp:UartCmp|Uart:uart|QueueCompatibility:rxQueue|ram" is uninferred due to asynchronous read logic File: /opt/t-crest/patmos/hardware/build/Patmos.v Line: 14823
...

[Emoun]

Please provide the link to the Reddit question.

Seems like we are dependent on an implementation detail (how Quatus infers stuff). Can we change the code to always use RAM regardless of Quatus version?

[epsilon-0311]

That is the link to the answer.

https://www.reddit.com/r/FPGA/comments/pop5ia/quartus_201_high_logic_cell_usage/hd2v38c?utm_medium=android_app&utm_source=share&context=3

The generated code looks like the example to me. I skimmed through the settings of quartus but nothing really catched my eye.

Edit:
I just posted a question on the intel support forums maybe we get some hints there https://community.intel.com/t5/Intel-Quartus-Prime-Software/Uninferred-ram-due-to-asynchronous-read-logic-Quartus-19-1-vs-20/m-p/1315819#M70854

[schoeberl]

Mmh, this is very bad. I guess/hope we can fix this when changing some of the Chisel code. We used a dedicated register and an asynchronous RAM, where Quartus 19 could infer a block RAM, which has a register input. Chisel has also a SyncRam, where the register is implicit. Maybe that would then work in Quartus 20.

[schoeberl]

I think we should do the forwarding manual ourself.

[schoeberl]

Added forwarding to all memories, which almost solves this issue. All memories are now mapped to on-chip memories except the data cache. Don't know what the difference is, as all caches use the same MemBlock module.