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4-way-set-associative-cache-verilog

Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy

4way-cache

Verilog cache implementation of 4-way FIFO 16k Cache

566_project

Source repository for 566 class project

a2

ahb-systemverilog

airblue_7dec12

airblue: trying to simulate the noisy channel and am getting "undefined symbol: gsl_rng_default" error

amba_axi3

System Verilog and Emulation. Written all the five channels.

antikernel

The Antikernel operating system project

antikernel-ipcores

FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations

aq_mipi_csi2rx_ultrascaleplus

atalanta

Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.

bch_verilog

Verilog based BCH encoder/decoder

cachesim

Cache system simulator for C++ and Verilog VPI.

can-bus-controller

An CAN bus Controller implemented in Verilog

chisel3

Chisel 3

cmos_linux

cnn_vgg19_verilog

Convolution Neural Network of vgg19 model in verilog

cocotb

Coroutine Co-simulation Test Bench

convolutional-neural-network

Implementation of CNN using Verilog

cordic

An implementation of the CORDIC algorithm in Verilog.

cores

Various HDL (Verilog) IP Cores

cpu_design

Verilog of a tapeout reprogrammable chip for analog circuit auto-tuning

cs231n-project

CNN accelerator

ddr2_controller

DDR2 memory controller written in Verilog

design-verification

Course content for the University of Bristol Design Verification course.

doc

Documentation for NVDLA.

doxverilog

Eric's branch of Doxverilog (doxygen + doxverilog patch)

dv_s2qed_riscv

Verification of RISC-V Processor Core(s) using S2QED. some formal code

dvi_lvds

DVI to LVDS Verilog converter

e200_opensource

The Ultra-Low Power RISC Core