The birds have vanished down the sky.
Now the last cloud drains away.
We sit together, the mountain and me,
until only the mountain remains.
Zazen on Ching-t’ing Mountain
A Clash playground/starter kit, using Nix
License: MIT License
The birds have vanished down the sky.
Now the last cloud drains away.
We sit together, the mountain and me,
until only the mountain remains.
Zazen on Ching-t’ing Mountain
There is an updated version of fetchnix.nix
here that describes a version that will properly work with Nix 2.0 (at the cost of requiring two hashes in nixpkgs.json
).
IIRC, the Xilinx Spartan 6 LX 9 is one of the few FPGAs on the market for which the workflow can be entirely based on open source software. It would be nice if this repository gave you all the tools necessary to do that workflow. In particular, I'm thinking that it might be worth optimizing the user experience for the Scarab Hardware miniSpartan6+. I ordered one, so I will probably make a pull request adding this feature once it arrives, but I figured I'd make an issue in case I don't get around to it.
I'm looking at doing a project with an iCE40-HX4K and Lattice.hs seems to be a good way to use iCE40 chips with Clash. Unfortunately clockGate was removed in the 1.0 release of Clash (I'm using 1.2.4), so Lattice.hs refuses to compile because of sbPll40
. I thought maybe I could just change unsafeCoerce (clockGate clk rst)
to unsafeCoerce clk
and remove the Reset
argument (in effect removing the reset capability), but the Reset
is returned from the function, so I can't do that either. Any ideas? I have little idea what clockGate
even does, to be honest, so I don't know how to replace it with Clash 1.2.4 concepts.
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