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timingan's Projects
abc
ABC: System for Sequential Logic Synthesis and Formal Verification
basejump_stl
BaseJump STL: A Standard Template Library for SystemVerilog
cosa
A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)
e3d
[ECCV 2020] Searching Efficient 3D Architectures with Sparse Point-Voxel Convolution, together with the fast GPU inference library for sparse convolution.
nn_dataflow
Explore the energy-efficient dataflow scheduling for neural networks.
rostam
simple-magic
SIMPLE MAGIC: Synthesis and In-memory MaPping of Logic Execution for Memristor Aided loGIC
ssproject_jumper
Platform for the Project Homework of Signal and System Lesson -- Wechat Jumper Game Robot
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