Essenceia/Nasdaq-HFT-FPGA
RTL design for a nasdaq compatible high frequency trading low level. Supports itch on moldudp64.
61 repositories
RTL design for a nasdaq compatible high frequency trading low level. Supports itch on moldudp64.
Production-grade low-latency FPGA trading system. Features custom VHDL 10GBASE-R PHY, hardware NASDAQ ITCH 5.0 order book, C++ DPDK/XDP kernel bypass, and PCIe DMA acceleration. LLM-Inference
MeatPy
Finance and Trading Protocols in Golang
Price response function and spread impact analysis in correlated financial markets
Parser for NASDAQ ITCH 5.0.
Hardware-accelerated (FPGA) HFT trading pipeline for NASDAQ TotalView-ITCH 5.0 market data. Implements an async FIFO, MoldUDP64 deframer, ITCH parser, L1/L2/L3 limit order book, and trade signal engine. SystemVerilog RTL verified in Verilator against a C++ golden model and running on a Xilinx ZCU104 at 240 MHz with 33 ns decision latency.
FPGA Nasdaq ITCH 5.0 feed handler and pipelined order book for the ZCU106, targeting 10GbE low-latency market data processing.
Nasdaq TotalView-ITCH 5.0 Parser
Market Data Feed Handler, ITCH Protocol. MoldUDP Multicast Useful for the new Mexican Stock Exchange BIVA (Bolsa Institucional de Valores) that uses X-Stream (NASDAQ).
BIVA MarketData ITCH Feed Handler Unicast SoupBinTCP BIVA MarketData ITCH Feed Handler Multicast MoldUDP BIVA MarketData ITCH Feed Handler Recovery UDP BIVA OrderRouting OUCH OMS Unicast SoupBinTCP BMV MarketData INTRA Feed Handler Multicast UDP BMV MarketData INTRA Feed Handler Recovery TCP Useful for the new Mexican Stock Exchange BIVA (Bolsa Institucional de Valores) that uses X-Stream (NASDAQ) and the Mexican Stock Exchange (Bolsa Mexicana de Valores)
Nasdaq OUCH 5.0 C libary
Fake nasdaq server C library used in testing FPGA HFT project
Parser for Nasdaq TotalView-ITCH 5.0
Market Data Feed Handler, ITCH Protocol. SoupBinTCP Unicast Useful for the new Mexican Stock Exchange BIVA (Bolsa Institucional de Valores) that uses X-Stream (NASDAQ).
Small C library to handle itch messages
An ITCH message parser implemented in Rust.
High-performance PCAP market-data decoder for exchange feeds, currently focused on NASDAQ TotalView-ITCH 5.0 and multi-symbol Level-3 order book reconstruction.
A high-performance, ultra-low latency C++17 trading infrastructure engine that parses raw NASDAQ ITCH 5.0 binary feeds and reconstructs real-time Limit Order Books (LOB) at ~7M msgs/sec using Zero-Copy mmap, Lock-Free SPSC queues, and Object Pooling.
A modular Python framework for extracting short-term alpha signals from high-frequency market data (e.g., NASDAQ ITCH), with integrated backtesting, ML model integration, and dashboard visualization.
An FPGA-accelerated High-Frequency Trading design on the Xilinx Zynq-7020 (PYNQ-Z2)
An ultra-low latency, O(1) limit order book written in C++20. Features zero-copy PCAP/ITCH network ingestion, lock-free ring buffers, and custom memory pools to achieve ~9ns per-order matching latency.
NASDAQ ITCH 5.0 parser Limit Orderbook websocket server
Implements multi-protocol market data parsing supporting NASDAQ (UDP/MoldUDP64), ASX (TCP/SoupBinTCP), and B3 Brazilian Exchange (UDP/SBE) market data feeds. Integrates with Project 33's 10GBASE-R PHY for 10GbE reception and outputs parsed messages via Aurora to FPGA2 (order book engine).
Low-latency NASDAQ ITCH 5.0 market-data ingestion engine consuming Ethernent/UDP/MoldUDP64 over DPDK, maintaining stateful consumers and dispatching top of book updates to strategies via a custom SPMC queue.
NASDAQ ITCH 5.0 feed handler + limit order book in SystemVerilog, diffed message-by-message against a C++ golden model over a full trading day: 268.7M messages, zero mismatches
Cycle-accurate C++20 FPGA tick-to-trade datapath simulator: 64b/66b PCS framing, zero-copy NASDAQ ITCH 5.0 parsing, a five-level order book, and a PCIe DMA model — zero heap allocation, zero std::chrono, on the hot path.
VSX: an electronic exchange in modern C++ - matching engine, ITCH replay, binary protocols, trading agents, live viz
Building a binary message decoder for ITCH 5.0
VHDL FPGA feed handler for NASDAQ TotalView-ITCH 5.0 over MoldUDP64/UDP/IPv4 — AXI-stream parsing, framing, and order extraction. Verified in ModelSim, synthesized for Quartus (171MHz) and Vivado (timing closed).