BlackBox clock + reset about chisel-tutorial

[Dolu1990]

After consulltation of source code, that's not possible to do that ".clk(clockA)"
because in verilog.scala :

def emitDef(c: Module): String = {
    ...
    if (c.clocks.length > 0) {
      res = res + (c.clocks).map(x => "." + emitRef(x) + "(" + emitRef(x) + ")").reduceLeft(_ + ", " + _)
    }

Somebody know if there is a plan for fix that ? if no, i can try to fix that with a pull request in the chisel repository.

[ben-k]

It seems like you're asking about support for multiple clock domains, which are now supported in Chisel. See Section 18 of the most recent Chisel manual.

I think the reset signal is global, though. You may want to post this comment as a feature request in the main Chisel repo (ucb-bar/chisel) if you want a more thorough response.

[Dolu1990]

Hi,
Thanks for answer : D

Multiple clock domaine is not well supported for black boxing because when you do multiple instance of a black box with different clock, that don't call the same verilog module : .clockA(clockA) in place of .blackBoxClockName(clockA)

For example now chisel do that :

  MyBlackBox_0 instA(.clockA(clockA), ... 
  );
  MyBlackBox_1 instB(.clockB(clockB), ... 
  );

That made 2 different verilog implementation of the same BlackBox juste because clock name change.

Reset was not realy my ask, but do a global reset in a multiple clock domaine design,where reset go directly to each flip flip is a bad idea. (Bad boot with setup and hold violation)

When i have post this issue, it was for new tutorial about that, but after that i realise that is a not supported feactures of chisel. With this consideration, it's true, this issue must move in chisel repo.