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vachanukb04's Projects

16-bit_cpu_design icon 16-bit_cpu_design

Designed, Simulated and Synthesized a 16-Bit CPU in Verilog HDL. The design involved RTL coding for counter, ALU, CPU controller, Instruction register and data memory.

32-bit-risc-v-based-cpu icon 32-bit-risc-v-based-cpu

Designed a 32-Bit RISC-V ISA based 5-Stage pipelined CPU in 5 days!! The design involved TL-Verilog coding for a simple pipelined calculator and addressed all the hazards.

512-bit-sram icon 512-bit-sram

Design of 512-Bit SRAM using four 128bits banks using Cadence Virtuoso

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