vanellope0602 Goto Github PK

5-stage-mips

5 Stage Pipelined MIPS Processor Implementation in Verilog

aplusbone

OO homework1

bertner_legal_pretrained

使用了Pre-trained Chinese ELECTRA，bert+BiLSTM+CRF的法律文书命名实体识别，进行交通肇事案的事件要素抽取

buaa_bluespec

北航高等计算机体系结构实验

buaa_complier

The compiler lab of BUAA (2019 Autumn)

buaa_mips_os

北航小操作系统实验代码lab1~lab6

cec-esteral

Columbia Esterel Compiler - Personal copy for archive

cnnvis-pytorch

visualization of CNN in PyTorch

crazyscaler

阿里云天池大赛-2023云原生编程挑战赛1：针对 Serverless 场景冷启动问题的弹性优化

cse723_esterelcode

Copy For Archive

data-structure-and-programming

The courses in my second semester in university

git-learn

None

groupchat_wechatapp

一款带课程群聊、知识分享、日程管理的微信小程序

lab_pda

A Push down Automata

leetcode

LeetCode Problems' Solutions

material-design-icons

Material Design icons by Google

mips-architecture-cpu-design

BUAA SCSE - Computer Organization - Pipeline CPU design

mips-single-cycle-cpu

P4 task of BUAA CO course

mipscpu

Fully pipelined MIPS CPU in Verilog/SystemVerilog with advanced branch prediction, register renaming, and value prediction

multi_elevator

The 7th homework of OO in BUAA, SS elevator

oo5_elevator1

FAFS

oohomework1

OO作业临时存放区

oohomework2

oohomework3

The last derivation in unit 1.

pipeline_cpu

P5 task of BUAA CO course

possible-solution-for-info-safety

software_engineering_calendar

A calendar web app that can regulate events using python flask

ustc-cs-courses-resource

:heart:**科学技术大学计算机学院课程资源(https://mbinary.coding.me/ustc-cs/)