Comments (3)
@AlexandreSinger Can this be related to your recent PR?
from vtr-verilog-to-routing.
@soheilshahrouz Yep... Sorry about that. See PR #2583
from vtr-verilog-to-routing.
@soheilshahrouz Yep... Sorry about that. See PR #2583
Thanks for the quick fix.
from vtr-verilog-to-routing.
Related Issues (20)
- Loosen the minimum channel width and related metric pass characteristics for small circuits HOT 1
- See if simplifying the placement cost function slightly would speed up placement.
- Document how to build for debugging HOT 2
- Missing documentaion for some 3D-related tags and fields in the architecture reference
- [Route] Precision Issues in the Connection Router HOT 6
- Relax when router lookahead issues warnings for failure to find sample locations HOT 6
- [CI] Nightly Test Failures HOT 2
- Passing only Fc max to pin to track map function HOT 8
- Placement Internals Document
- Placement `channel_width_fac`
- [CI] Investigating CI Runners HOT 5
- Remove +1 from wirelength estimate HOT 1
- Fc_override Not Parsed Correctly HOT 1
- Koios Benchmarks Failing With Flat Routing HOT 1
- VPR warning verbosity with timing analysis on and custom routing graphs with isolated clock routing
- VTR format checking / auto-format not checked by CI?
- Make a short coding style guide in the VTR developer guide
- vtr optional documentation showing up at the top of vtr::vector and vtr::vector_map documentation HOT 1
- redundant adders when synthesizing addition with full adders HOT 2
- Placement Constraints not working HOT 6
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