Comments (16)
I want to consider it, but I think the priority is low.
from veryl.
Does Expression in case item have no problem for synthesis?
Yes. In fact, our RTL includes this kind of code.
from veryl.
Do you plan to add case inside
feature?
from veryl.
Instead of default
, How about Rust style default?
always_ff (clk) {
case x {
0: a = 1;
1: a = 2;
2: {
a = 3;
b = 4;
}
_: a = 4;
}
}
from veryl.
In SysemVerilog, ?
and *
are used as symbols which mean wildcard. For exmaple: wildcard operator ==?
, wildcard index type int a[*]
.
How about using ?
or *
instead of _
?
from veryl.
I thought default
may be a little long. but there is not another problem.
So I'll use default
to follow SystemVerilog.
Do you have any other reason to change to ?
or *
?
from veryl.
I simply proposed ?
and *
as an alternative of _
character. So I have no special reason.
from veryl.
OK. I'll use default
at this time.
from veryl.
How about introducing case expression less case statement.
Example:
case {
foo: a = 1;
bar: a = 2;
default: a = 3;
}
Equivalent code:
case 1 {
foo: a = 1;
bar: a = 2;
default: a = 3;
}
This idea is originally from Ruby's case expression.
from veryl.
It looks good. Does Expression in case item have no problem for synthesis?
from veryl.
Expression less case seems to be difficult to parse by LL(k).
This is because
case { <- Is this `{` case body's start or expression with concatenation?
foo: a = 1;
}
To avoid this, chanigning case
keyword for expression less case is required.
from veryl.
I don't care if expression less case feature is not introduced because I just put 1
as a case expression.
from veryl.
I feel case 1
may be bit strange, but I have no idea about alternative keyword.
So I'll keep the current implementation until new idea.
from veryl.
Introduce other keyword insead of case
? For example, switch
, branch
..?
from veryl.
switch
seems to be good.
from veryl.
The idea of switch
statement moved to #643.
from veryl.
Related Issues (20)
- Raw identifier
- SystemVerilog keyword check HOT 2
- Clock domain annotation
- Test written in veryl has the module in the ifdef line HOT 1
- [Feature] Default value of generics parameter
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- Semantic error checker flags non-real errors HOT 3
- Check overlapping of multiple partial assignment
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- Function identifier refered as a factor
- Generics arity error inside generic package HOT 3
- Confusing error message when simulator binary is not found
- Undefined identifier error for generic type argument
- Type name and variable name conflicts cause stack overflow HOT 1
- Undefined identifier error is duplicated
- Panic on resolving generics parameters
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from veryl.