Comments (2)
::
can be used for project namespace resolver like package.
[dependencies]
prj1 = { git = "" }
module ModuleA {
inst a: prj1::ModuleB;
}
In SystemVerilog, ::
is replaced with _
.
module ModuleA;
prj1_ModuleB a();
endmodule
from veryl.
Project name should be added too.
[project]
name = "sample"
[dependencies]
prj1 = { git = "" }
module ModuleA {
inst a: prj1::ModuleB;
}
module sample_ModuleA;
prj1_ModuleB a();
endmodule
from veryl.
Related Issues (20)
- Raw identifier
- SystemVerilog keyword check HOT 2
- Clock domain annotation
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- [Feature] Default value of generics parameter
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- Semantic error checker flags non-real errors HOT 3
- Check overlapping of multiple partial assignment
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- Function identifier refered as a factor
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- Undefined identifier error is duplicated
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from veryl.