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2020-sram-training-course

Memory Compiler Tutorial

ahb3_uvm_tb

AMBA 3 AHB UVM TB

amba-3-ahb--lite-protocol-design-and-verification

-Designed and Verified a Bus Functional Model of AHB-LITE Protocol from scratch. -Developed Assertion based verification IP to verify the bus and check for protocol violations. -Implemented constraint randomization and OOPs verification techniques.

dmips

Original MIPS implementation in Verilog based on Tiny MIPS.

modica-sram

Design of a 32-kbit synchronous SRAM with 32-bit words, using 180 nm process technology. Developed MATLAB scripts to evaluate architectural trade-offs between performance (using logical effort analysis) and area usage; see the source code for the HSPICE decks and MATLAB scripts that are used during architectural trade-off evaluation, and characterization of inverters for different supply voltages (VDD) and temperatures. It also includes HSPICE decks for the characterization of the 6-transistor SRAM cell for different transistor ratios, and the SRAM read and write circuitry. Co-designed and co-developed the SRAM using schematic entry in Cadence Virtuoso. Performed functional and timing verification by simulating extracted SPICE netlist in NanoSim.

physical-design-and-verification-of-dpram-using-sv-uvm-and-semi-custom-design

Memory Level Verification of Dual Port RAM using SystemVerilog and Universal Verification Methodology Environments with assertions,functional coverage and code coverage report

sram

The Verilog model for SRAM IS61WV102416 chip with timings

sva-based-verification-of-ahb-lite-protocol

system-bus-design-verilog

This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification

types-of-verification-using-sram

This repo contains golden vector and randomization testbenches for SRAM module.

uvm_axi-4-

uvmprimer

Contains the code examples from The UVM Primer Book sorted by chapters.

verilog-axi

Verilog AXI components for FPGA implementation

vlsiuser

Config files for my GitHub profile.