- š Hi, Iām @vlsiuser
- š Iām interested in ...vlsidesign verification
- š± Iām currently learning ...verilog
- šļø Iām looking to collaborate on ...
- š« How to reach me ...
vlsiuser Goto Github PK
Type: User
Type: User
Memory Compiler Tutorial
AMBA 3 AHB UVM TB
-Designed and Verified a Bus Functional Model of AHB-LITE Protocol from scratch. -Developed Assertion based verification IP to verify the bus and check for protocol violations. -Implemented constraint randomization and OOPs verification techniques.
Original MIPS implementation in Verilog based on Tiny MIPS.
Design of a 32-kbit synchronous SRAM with 32-bit words, using 180 nm process technology. Developed MATLAB scripts to evaluate architectural trade-offs between performance (using logical effort analysis) and area usage; see the source code for the HSPICE decks and MATLAB scripts that are used during architectural trade-off evaluation, and characterization of inverters for different supply voltages (VDD) and temperatures. It also includes HSPICE decks for the characterization of the 6-transistor SRAM cell for different transistor ratios, and the SRAM read and write circuitry. Co-designed and co-developed the SRAM using schematic entry in Cadence Virtuoso. Performed functional and timing verification by simulating extracted SPICE netlist in NanoSim.
Memory Level Verification of Dual Port RAM using SystemVerilog and Universal Verification Methodology Environments with assertions,functional coverage and code coverage report
The Verilog model for SRAM IS61WV102416 chip with timings
This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification
This repo contains golden vector and randomization testbenches for SRAM module.
Contains the code examples from The UVM Primer Book sorted by chapters.
Verilog AXI components for FPGA implementation
Config files for my GitHub profile.
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Open source projects and samples from Microsoft.
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Data-Driven Documents codes.
China tencent open source team.