vrajeshprakhya/spice2rnm-demos
Customer walkthroughs of the spice2rnm pipeline: LPF, duty-cycle corrector, phase interpolator
Repositories
vrajeshprakhya/ams-cosim
Lockstep co-simulation between ngspice (SPICE netlist) and xezim (SystemVerilog RTL)
vrajeshprakhya/OpenVAF-Reloaded
OpenVAF revived by community
vrajeshprakhya/xezim
Open-source SystemVerilog simulator in Rust. 4-state, event-driven, IEEE 1800-2023, runs real UVM.
vrajeshprakhya/xezim-core
SystemVerilog Frontend for simulator