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algebraic-nnhw

AI acceleration using matrix multiplication with half the multiplications

amba_axi_ahb_apb

AMBA bus lecture material

arm_amba_design

Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

axis-async-fifo

parameterized AXIS FIFO design

cdc_fifo_design

Multi-bit Synchronization across Clock Domains

clacc

Deep Learning Accelerator (Convolution Neural Networks)

cnn-fc-accelerator

Basic convolutional neural network and fully connected layer accelerator

deepfloat

An exploration of log domain "alternative floating point" for hardware ML/AI accelerators.

digital-flow

This is a tutorial on standard digital design flow

dynamic-branch-predictor-in-pipelined-processors

ethernettimesynchronizer

examples

fir-filter

FIR Filter Add/Shift implementation using Inverted form

gemmini

Berkeley's Spatial Array Generator

gen_amba_2021

AMBA bus generator including AXI4, AXI3, AHB, and APB

halutmatmul

Hashed Lookup Table based Matrix Multiplication (halutmatmul) - Stella Nera accelerator

hardware-matrix-multiplication-accelerator

Hardware Matrix Multiplication Accelerator (Verilog RTL)

hpdla

Systolic-array based Deep Learning Accelerator generator

hw

RTL, Cmodel, and testbench for NVDLA

hw_interview_questions

A collection of commonly asked RTL design interview questions

infinite-isp

A camera isp (image signal processor) pipeline that contains modules with simple to complex algorithms implemented at the application level.

infinite-isp_referencemodel

A Python based fixed-point implementation of the Infinite-ISP design for ASIC and FPGA design and verification.

isp-guide

Image Signal Processing (ISP) Guide

isp-pipeline-hdrplus

Denoise,HDR,Isppipeline,Image-processing(图形处理),camera, Isp ,HDRplus

low-speed-controllers

I2C, SPI, UART memory bridge

matrix-multiplication

Accelerator for Floating Point Matrix Multiplication

mips-5-stage-pipelined-control-and-datapath

Implementation of a 32-bit 5 stage Pipelined MIPS Processor using RTL coding in Verilog on ModelSim simulator. The processor datapath and control units are designed for Arithmetic and Logical instructions (all r-type instructions + addi, andi, ori, slti), Data transfer instructions (lw, sw), Branch and jump instructions (beq, j). Forwarding control

mxn-cross-bar-switch

Axis based MxN cross bar switch implementation

nand-flash-controller

2, 4, 8Gb: x8/x16 Multiplexed NAND Flash Memory