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advanced-uvm-hawkins

advanced-uvm-second_edition

Code for the second edition of Advanced UVM.

ahb-tl-bridge

SystemVerilog implementation of the AHB to TileLink UL (Uncached Lightweight) bridge

apb_spi_master

ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

arm-syntax-vim

ARMv4 through 7 syntax highlighting for vim

arm64-pgtable-tool

Tool for automatically generating MMU and translation table setup code, whether to drag and drop into your own bare metal arm64 projects or to assist you in your own learning.

arm64asm-vim

AArch64 (ARM64) Assembly Syntax Highlighting (for VIM)

axi_spi_master

axi_spi_slave

basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog

bash-scripts

Usefull bash scripts for various tasks

bender

A dependency management tool for hardware projects.

bsub

python wrapper to submit jobs to bsub (and later qsub)

caliptra-rtl

HW Design Collateral for Caliptra RoT IP

cocotbext-pcie

PCI express simulation framework for Cocotb

common_cells

Common SystemVerilog components

config_policy_pattern

Support code for DVCon 2021 paper submission

core-v-cores

CORE-V Family of RISC-V Cores

core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

corstone700

Docker environment to build and run the Corstone-700 software on the Fixed Virtual Platform (FVP)

cosim-arch-checker

Framework to perform DUT vs ISS (Whisper) lockstep architectural checks

cshenv

My personal TCSH login scripts and vimrc files.

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

design-verification

Course content for the University of Bristol Design Verification course.

dotfiles

vim dotfiles for asic

embedded-iot_profile

embedded-iot_profile

fixsegfaultvcs

There is segmentation fault of VCS which should be fixed.

fm-peripheral

Examples for creating Arm Fast Model peripherals

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development