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Icser's Projects

awesome-paper icon awesome-paper

The trace of Paper Reading about DSA、GPU、LLM and AI System

b-core icon b-core

a five stage riscv core using SpinalHDL and some common libs

b-lib icon b-lib

some useful libs using in the SpinalHDL

betsy icon betsy

The Implement of the Systolic Array Accelerator

brief-chip icon brief-chip

The Brief Chip is a Simple Soc project written in Spinal HDL , include a 3 stages RISCV CPU and a CNN Accelerator with RS Dataflow as Peripheral

gpgpu icon gpgpu

The trace to study in the GPU Arch and Cuda Programming

ictools icon ictools

Here is some really useful tools for the ASIC/FPGA Design

math icon math

SpinalHDL Hardware Math Library

neural-networks-on-silicon icon neural-networks-on-silicon

This is originally a collection of papers on neural network accelerators. Now it's more like my selection of research on deep learning and computer architecture.

openrpdk28 icon openrpdk28

Open source process design kit for 28nm open process

opentpu icon opentpu

A open source reimplementation of Google's Tensor Processing Unit (TPU).

rvgenerator icon rvgenerator

use to generate the random RISC-V instructions to test the CPU

spatten-llm icon spatten-llm

[HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning

stylepatch icon stylepatch

the source code of the StylePatch(a adversarial patch attack method using the local style fusion)

tensil icon tensil

Open source machine learning accelerators

tvm icon tvm

Open deep learning compiler stack for cpu, gpu and specialized accelerators

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