yimingao0113 Goto Github PK

artys7-rpu-soc

Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board.

black-parrot

A Linux-capable RISC-V multicore for and by the world

blog

My blog :)

chatroomapp

🥴A web chatroom app

cs-notes

:books: 技术面试必备基础知识、Leetcode、计算机操作系统、计算机网络、系统设计

embedded_system

fifo

Generic FIFO implementation with optional FWFT

firmware-syntiant-tinyml

Edge Impulse firmware for Syntiant TinyML board

github-clone-all

Clone (~1000) repos matched to query on GitHub using Search API

iverilog

Icarus Verilog

learn-fpga

Learning FPGA, yosys, nextpnr, and RISC-V

leetcode

😏 LeetCode solutions in any programming language | 多种编程语言实现 LeetCode、《剑指 Offer（第 2 版）》、《程序员面试金典（第 6 版）》题解

litex

Build your hardware, easily!

litex-boards

LiteX boards files

minidiscord

A mini discord server 😋

mnist-cnn-99.5

nitro-parts-lib-spi

Verilog SPI master and slave

openroad-flow-scripts

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

rops

Rock Paper Scissor game for the NAO robot to improve human rhythm perception

serv

SERV - The SErial RISC-V CPU

simd_multipliers

spi

SPI protocol modules in SystemVerilog

spi_master

subservient

Small SERV-based SoC primarily for OpenMPW tapeout

super_spi_master_verilog

SPI Master Verilog module

tt06-verilog-template

Submission template for Tiny Tapeout 06 - Verilog HDL Projects

uart_tx

A simple uart project implemented on FPGA

uxlp

uxlp2

verilog-uart

Verilog UART