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yuanerandlee2's Projects

30-seconds-of-python

Short Python code snippets for all your development needs

arl

lists of most popular repositories for most favoured programming languages (according to StackOverflow)

basic_verilog

Must-have verilog systemverilog modules

corundum

Open source, high performance, FPGA-based NIC

cpu-rtl

Verilog HDL-CPU

darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

dpdk

Data Plane Development Kit

fpga

FPGA

fpgaandlan

FPGAandLAN

hw

RTL, Cmodel, and testbench for NVDLA

nyuziprocessor

GPGPU microprocessor architecture

opentitan

OpenTitan: Open source silicon root of trust

openwifi

open-source IEEE802.11/Wi-Fi baseband chip/FPGA design

py-icehappy

利用Python3和Pygame开发的一款桌面端消消乐游戏，本项目使用分文件的构建方式，自主设计和编写了消除、交换、判断是否为可消除图等算法，并自行担任UI设计，实现了开心消消乐的选择关卡、金币、步数、消除、随机分配消除块等基本功能。

riffa

The RIFFA development repository

swerv_eh1

A directory of Western Digital’s RISC-V SweRV Cores

systemverilogassertions

Examples and reference for System Verilog Assertions

systemverilogreference

training labs and examples

ustc-rvsoc

FPGA-based RISC-V CPU+SoC.

uvm_axi

uvm AXI BFM(bus functional model)

uvmreference

Reference examples and short projects using UVM Methodology

verilog-axi

Verilog AXI components for FPGA implementation

verilog-cam

Verilog Content Addressable Memory Module

verilog-ethernet

Verilog Ethernet components for FPGA implementation

verilog-i2c

Verilog I2C interface for FPGA implementation

verilog-pcie

Verilog PCI express components

verilog-uart

Verilog UART

wujian100_open

IC design and development should be faster，simpler and more reliable

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