Open Source Chip Project by University (OSCPU)
Zhoushan is a 2-way superscalar out-of-order core, compatible with RV64I ISA.
Main developer: Li Shi (SJTU/CMU ECE)
-
AM, branch: zhoushan
-
AM-Kernels, branch: master
-
NEMU, branch: master
-
ESPRESSO, branch: master
First, download all the dependency repositories and set the environment variables as follows.
export NOOP_HOME=<...>/Zhoushan
export NEMU_HOME=<...>/NEMU
export AM_HOME=<...>/abstract-machine
export DRAMSIM3_HOME=<...>/Zhoushan/DRAMsim3
Then, config and make NEMU
and DRAMsim3
, and install ESPRESSO
.
To generate Verilog:
make
To build and run the binary for emulation and difftest:
make emu
./build/emu -i path/to/risc-v/binary.bin
To run functional tests:
./test.sh -c
./test.sh -r
-
Bus ID is set in
ZhoushanConfig
. -
Bus ID must start from 1, and should not skip any index. Bus ID must match the order of
CrossbarNto1
.
-
Branch for dev:
dev/XxxYyy
. Example:dev/ScalarPipeline
,dev/Superscalar
. -
Only merge stable version (passing all tests) to
develop
branch after being permitted by Li Shi. -
Never push or merge to
master
branch directly. Make a pull request.
Filename & class/object/trait name & constant: CamelCase (even though it contains abbreviation, e.g., we write BhtWidth
rather than BHTWidth
). Example:
// SimTop.scala
class SimTop extends Module {
...
}
// ZhoushanConfig.scala
trait ZhoushanConfig {
// MMIO Address Map
val ClintAddrBase = 0x02000000
...
}
Function name: camelCase. Example:
def getFlag(x: UInt): Bool = x(addr_width - 1).asBool()
Wire, register, instance, io name: some_name. Example:
val this_wire = ...
val this_module = Module(new ThisModule)