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5-stage-pipelined-cpu

CSC3050

accdnn

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

accel_aes

aes-128_pipelined_encryption

AES-128 Encryption

aes-fpga

AES加密解密算法的Verilog实现

ahb2

AMBA AHB 2.0 VIP in SystemVerilog UVM

ahb5

AMBA AHB 5.0 VIP in SystemVerilog based on UVM

ak-cmsis-dap

AK-CMSIS-DAP JTAG/SWD

amba-3-ahb-lite-protocol

This Repo contains SystemC for testBench for AMBA® 3 AHB-Lite Protocol

amba-vip

All AMBA bus protocols - AXI3, AXI4, AXI4-Lite, ACE, AHB

amba3-vip

amba3 apb/axi vip

amba_apb_sram

AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).

amba_axi_ahb_apb

AMBA bus lecture material

amiq_apb

SystemVerilog VIP for AMBA APB protocol

arm_m3_design

personal practice

arty-cm0-designstart

A port of the DesignStart Cortex-M0 system to the Diligentinc Arty board

awesome-riscv

😎 A curated list of awesome RISC-V implementations

axi-crossbar

An AXI4 crossbar implementation in SystemVerilog

axiprotocol-through-fifo

This Project aims to design the working of AMBA Bus Architechture, considering the AXI protocol. AXI protocol defined for high-frequency, high-bandwidth systems for data communication.

biriscv

32-bit Superscalar RISC-V CPU

buaa_co

2017级北航计算机学院计算机组成原理课程设计(MIPS CPU)

buaa_course_sharing

北京航空航天大学(北航)课程作业资料共享计划

cmsis-dap

STM32 port for CMSIS-DAP with additional serial (CDC) support

cmsis_5

CMSIS Version 5 Development Repository

cnn-accelerator

DMA controller for CNN accelerator

computer_organization

計算機組織 mips/fpa/riscv_cpu/cache

control-unit-noise-cancellation-system

Control unit for Noise Cancellation System. Built in Verilog.

core_ddr3_controller

A DDR3 memory controller in Verilog for various FPGAs

cores

Various HDL (Verilog) IP Cores

cores-swerv

SweRV EH1 core