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5gpolar

Polar encoding & decoding

accelerating-cnn-with-fpga

This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.

accelergy

Accelergy is an energy estimation infrastructure for accelerator energy estimations

ai

Repo for work for AI Survey

awesome-blockchain-cn

收集所有区块链(BlockChain)技术开发相关资料，包括Fabric和Ethereum开发资料

awesome-eda

awesome-python-login-model

😮python模拟登陆一些大型网站，还有一些简单的爬虫，希望对你们有所帮助❤️，如果喜欢记得给个star哦🌟

bachelarbeit

bigdata

💎🔥大数据学习笔记

blephytracking

Repository of code for BLE physical-layer location tracking project

chisel

Chisel: A Modern Hardware Design Language

cmake

Mirror of CMake upstream repository

cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

cocotb-ahb

cocotb-tilelink

cocotbext-pcie

PCI express simulation framework for Cocotb

convolution_network_on_fpga

CNN acceleration on virtex-7 FPGA with verilog HDL

core

:cloud: ownCloud web server core (Files, DAV, etc.)

cores-veer-eh1

VeeR EH1 core

cores-veer-eh2

corundum

Open source FPGA-based NIC and platform for in-network compute

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

cx

Proposed RISC-V Composable Custom Extensions Specification

cxlmemsim

A place to store the CXL simulator

cxlpapers

datc-rdf-calibrations

ddr4memorycontroller

HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.

depix

Recovers passwords from pixelized screenshots

e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

f32c

A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.62 DMIPS/MHz