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advanced-physical-design-using-openlane-sky130-overview

face_mask_detection

open-source-rtl-design

This repository contains overview of things carried out during VSD "RTL Design Using Verilog With SKY130 Technology" workshop

openlane-skywater130-workshop

This repository aims to capture the works done in 5-day workshop of Adavance Physical Design using OpenLANE/SkyWater130. The workshop helps to familiarise with the efabless OpenLANE VLSI design flow RTL2GDS and the Skywater 130nm PDK.

opensource_physical_design

This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK

risc-v-core

This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover

risc-v-core-4-stage

risc-v_core_4_stage

RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set

rtl_design_workshop

This is a repository on RTL Design using Verilog with Sky130 Technology

rtldesignusingverilogwithsky130technology

RTL design using Verilog with SKY130 Technology. This is a 5-Day online workshop conducted by VLSI System Design, Banglore from 26th-30th May 2021. Learn basics of digital design using Verilog language, various RTL coding styles, typical synthesis problems faced by the industry, and how to solve them in Verilog.

sky130-rtl-design-workshop

VSD Workshop on RTL Design using Verilog HDL and Synthesis with Optimization using SKY130 Technology

verilog-rtl-design-using-sky130