LC3 Architecture and Assembly codes Test
This Project Contain The Desing and architecure of LC3 micro-processor with samples codes in assembly .
In this project i'm using Logisim to Design and Simulate LC3 Processosr.
you can download Logisim from this Link :
http://www.cburch.com/logisim/download.html
and you can download LC3 simulator from this Link:
http://www.cis.upenn.edu/~milom/cse240-Fall05/handouts/lc3guide.html
LC3-instructions :
| Syntaxe | Action | nzp | Codage | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Op-code | Arguments | |||||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
| NOT DR,SR | DR ← not SR | * | 1 0 0 1 | DR | SR | 1 1 1 1 1 1 | ||||||||||||
| ADD DR,SR1,SR2 | DR ← SR1 + SR2 | * | 0 0 0 1 | DR | SR1 | 0 | 0 0 | SR2 | ||||||||||
| ADD DR,SR1,Imm5 | DR ← SR1 + SEXT(Imm5) | * | 0 0 0 1 | DR | SR1 | 1 | Imm5 | |||||||||||
| AND DR,SR1,SR2 | DR ← SR1 and SR2 | * | 0 1 0 1 | DR | SR1 | 0 | 0 0 | SR2 | ||||||||||
| AND DR,SR1,Imm5 | DR ← SR1 and SEXT(Imm5) | * | 0 1 0 1 | DR | SR1 | 1 | Imm5 | |||||||||||
| LEA DR,label | DR ← PC + SEXT(PCoffset9) | * | 1 1 1 0 | DR | PCoffset9 | |||||||||||||
| LD DR,label | DR ← mem[PC + SEXT(PCoffset9)] | * | 0 0 1 0 | DR | PCoffset9 | |||||||||||||
| ST SR,label | mem[PC + SEXT(PCoffset9)] ← SR | 0 0 1 1 | SR | PCoffset9 | ||||||||||||||
| LDR DR,BaseR,Offset6 | DR ← mem[BaseR + SEXT(Offset6)] | * | 0 1 1 0 | DR | BaseR | Offset6 | ||||||||||||
| STR SR,BaseR,Offset6 | mem[BaseR + SEXT(Offset6)] ← SR | 0 1 1 1 | SR | BaseR | Offset6 | |||||||||||||
| LDI DR,label | DR ← mem[mem[PC + SEXT(PCoffset9)]] | * | 1 0 1 0 | DR | PCoffset9 | |||||||||||||
| STI SR,label | mem[mem[PC + SEXT(PCoffset9)]] ← SR | 1 0 1 1 | SR | PCoffset9 | ||||||||||||||
| BR[n][z][p] label | Si (cond) PC ← PC + SEXT(PCoffset9) | 0 0 0 0 | n | z | p | PCoffset9 | ||||||||||||
| NOP | No Operation | 0 0 0 0 | 0 | 0 | 0 | 0 0 0 0 0 0 0 0 0 | ||||||||||||
| JMP BaseR | PC ← BaseR | 1 1 0 0 | 0 0 0 | BaseR | 0 0 0 0 0 0 | |||||||||||||
| RET (≡ JMP R7) | PC ← R7 | 1 1 0 0 | 0 0 0 | 1 1 1 | 0 0 0 0 0 0 | |||||||||||||
| JSR label | R7 ← PC; PC ← PC + SEXT(PCoffset11) | 0 1 0 0 | 1 | PCoffset11 | ||||||||||||||
| JSRR BaseR | R7 ← PC; PC ← BaseR | 0 1 0 0 | 0 | 0 0 | BaseR | 0 0 0 0 0 0 | ||||||||||||
| RTI | cf. interruptions | 1 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 | |||||||||||||||
| TRAP Trapvect8 | R7 ← PC; PC ← mem[Trapvect8] | 1 1 1 1 | 0 0 0 0 | Trapvect8 | ||||||||||||||
| Reserved | 1 1 0 1 | |||||||||||||||||
