Thomasb81/xezim
SystemVerilog (IEEE 1800-2017) Simulator
Repositories
Thomasb81/xezim-core
SystemVerilog Frontend for simulator
Thomasb81/uhdm2rtlil
Yosys SystemVerilog Parser - UHDM 2 RTLIL Yosys Pass
Thomasb81/Midi_SynthFpga
Sound synthetizer with an fpga
Thomasb81/UHDM
Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
Thomasb81/adaptagrams
Libraries for constraint-based layout and connector routing for diagrams.
Thomasb81/xsdata
Naive XML & JSON Bindings for python
Thomasb81/planarity
Planar graph algorithms
Thomasb81/simpleparse
SimpleParse parser generator using mxTextTools (launchpad mirror)
Thomasb81/hdlConvertor
verilog and vhdl parser module for python
Thomasb81/dunnart
Constraint-based diagram editor
Thomasb81/adaptagram2
Thomasb81/grammars-v4
Grammars written for ANTLR v4; expectation that the grammars are free of actions.
Thomasb81/antlr4
ANTLR (ANother Tool for Language Recognition) is a powerful parser generator for reading, processing, executing, or translating structured text or binary files.
Thomasb81/cocotbext-ahb
Cocotb AHB Extension - AHB VIP
Thomasb81/sv-tests
Test suite designed to check compliance with the SystemVerilog standard.
Thomasb81/nanobind
nanobind — Seamless operability between C++17 and Python
Thomasb81/WeasyPrint
The awesome document factory
Thomasb81/elkjs-svg
Thomasb81/Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API.
Thomasb81/jinja
A very fast and expressive template engine.
Thomasb81/myhdl
The MyHDL development repository
Thomasb81/ZIA
ZIA Code Repository
Thomasb81/verilog-arbiter
A look ahead, round-robing parametrized arbiter written in Verilog.
Thomasb81/SD_spi
SPI / SDCard through serial controler experiment
Thomasb81/SDCard-PG
SD Card play ground
Thomasb81/ZPUino-HDL
ZPUino HDL implementation