An open-source SystemVerilog simulator, written in Rust.
RTL, gate-level and UVM simulation in one command, from source to results.

User guide · Command line · UVM · DPI & VPI · Release notes · Contributing

The feature list has the details.

xezim reads Verilog and SystemVerilog source files and simulates them. It preprocesses and parses the sources, elaborates the design hierarchy, compiles processes and continuous assignments into bytecode, and runs them on an event-driven kernel that follows the IEEE 1800 scheduling semantics. Most logic runs on fast two-state executors, which fall back to full four-state evaluation wherever x and z values appear.

Everything happens in one invocation, so a design goes from source to results without a separate build step, and a test suite made of many short runs gets its answers quickly. The same command line works for an RTL unit test, a gate-level netlist with SDF timing, or a full UVM environment.

git clone https://github.com/aionhw/xezim.git
cd xezim
cargo build --release          # or ./scripts/build-pgo.sh for a profile-guided build

// counter.sv
module counter_tb;
  logic clk = 0, rst = 1;
  logic [3:0] count;
  always #5 clk = ~clk;
  always_ff @(posedge clk) count <= rst ? '0 : count + 1;
  initial begin
    #12 rst = 0;
    repeat (3) @(posedge clk) $display("t=%0t count=%0d", $time, count);
    $finish;
  end
endmodule

$ ./target/release/xezim counter.sv
t=15 count=0
t=25 count=1
t=35 count=2
Simulation finished at time 35 ($finish called)

A UVM testbench needs only the UVM sources on the command line:

xezim -s top -I $UVM/src $UVM/src/uvm_pkg.sv <design and testbench files> \
      +UVM_TESTNAME=my_test

See the user guide and the UVM guide for more.

Whole-run wall-clock time on one machine (Intel Core i7-9800X, 6 cores, Linux): xezim 0.11 as a plain release build, against a commercial reference simulator in its optimized mode (no debug visibility). Both simulators produce the same results on every row.

• xezim starts fast. Compiling and elaborating is a small part of a run, so short tests and suites of many runs favour xezim.
• On long runs the reference kernel is faster, about 2× in the simulation phase on the C906, and more on long UVM runs. Closing this gap is where current work goes: since 0.11, host instructions are down 7% on CoreMark and on the AXI4 AVIP and 11% on the C910 memcpy, and peak memory on the C906 CoreMark run is down from 2.6 GB to 0.6 GB (see the release notes).

To get the most out of a build, use the profile-guided build (up to 14.5% fewer instructions when trained on your own workload) and keep the warm design cache on. Native compilation pays on designs with few, very hot blocks (Ibex CoreMark −23%), so measure it on yours.

• sv-tests: xezim 0.11.0 passes 4,722 of 4,770 tests (99.0%) of the sv-tests suite.
• UVM: the mbits-mirafra AVIP base tests for AXI4, APB, I3C, SPI and AXI4-Lite print the same UVM messages as a commercial reference simulator, and 32 of 35 UVM 1800.2-2017 example testbenches pass.
• Regression suite: more than 3,200 tests, run in CI with and without the JIT. Many are differential tests whose expected values were measured on a commercial reference simulator; see CONTRIBUTING.md.

Questions, bug reports and feature requests go to GitHub issues. A small self-checking testcase gets a bug fixed fastest; see CONTRIBUTING.md for what to include. Pull requests are welcome.

xezim explores whether modern tools and AI assistance can sharply reduce the cost of building core EDA infrastructure such as a simulator: work that has traditionally taken large teams many years. It was built incrementally, from simple combinational logic up to SoCs and UVM environments, with every step verified against the language standard and against a commercial reference simulator. Longer term, the project looks at cloud-scale and distributed multi-CPU simulation.

The project was previously developed under the name sisSIM.

Thank you to everyone who has improved xezim through pull requests:

• Thomas Burg — class-system and UVM fixes: static-property chains through object handles (§8.25), associative-array method dispatch and ref-writeback, ClassName::static_prop access, parser-gap self-tests, test-harness hardening, per-process bookkeeping for methods that park mid-body, the condition-waiter drain de-duplication, and the NBA-region lane in the --max-time hang report.
• Vrajesh Prakhya — real-number modelling: Verilog-AMS wreal nets resolved by summing, user-defined nettypes across the hierarchy and in packages (§6.6.7, §6.6.8), real-ness of members projected from call results, negative-test registrations, and the diagnosis that cover property sites were tallied as failing assertions.
• Oscar Gustafsson — expanded VPI functionality (vpi_get_value, ObjectValType), CI setup, and clippy cleanups.
• Chen Ben Haroosh — submodule-inline generate-for elaboration: genvar- dependent declarations and parameter type default resolution, plus the accompanying SystemVerilog compliance cases.
• Jayaraman RP — cross-platform installation scripts, including the macOS installer with UVM setup.
• Ganesh T S — wide-number parsing for $sscanf/$fscanf/$value$plusargs and the string conversion methods (arbitrary-precision decimal in the core), loop-variable scoping against same-named identifiers in child instances, and detailed self-checking bug reports for struct and class member access.
• eenky — declared defaults for parameters a class leaves out when it extends a parameterized class, and virtual-interface reads through class-handle chains (cfg.vif.data).
• Francesco Urbani — +incdir+ directories in -F args files resolved against the args file's own directory.

New contributors are welcome; see CONTRIBUTING.md.

• The Icarus Verilog project, for its public test suite
• The sv-tests project
• The Rust community and the open-source EDA projects xezim builds on

xezim is free software, licensed under the Apache License 2.0.