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View Code? Open in Web Editor NEWFPGA Acceleration of Secure Function Evaluation
FPGA Acceleration of Secure Function Evaluation
Hello, I'm excited to try FASE but currently running into the following error while implementation on Vivado:
[Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
Environment:
Freq:
In addition, I read in the paper that FASE operates at 200 MHz and I would like to replicate it.
Any help in figuring out a solution to this issue would be appreciated.
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