akashtailor-exe / 30-days-of-verilog

30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!

30 Days of Verilog

Repo was not updated daily. I posted consistently on Linkedin

Embark on a journey through 30 days of Verilog exploration! 🌟

Welcome to my personal project: 30 Days of Verilog. Over the next 30 days, I'll be taking a deep dive into the world of digital circuits and Verilog programming. My goal is to create and showcase 30 different digital circuits, each implemented using Verilog HDL.

About the Project

The aim of this project is to:

• Learn Verilog: Gain a solid understanding of Verilog and its applications.
• Explore Digital Circuits: Create a variety of digital circuits to explore different concepts.
• Document Progress: Document my journey, challenges, and solutions for each circuit.
• Share with the Community: Provide a resource for others interested in Verilog and digital design.

Repository Structure

Each day, I will add a new folder from Day 1 to Day 30, containing:

• Verilog Code: Implementation of the day's digital circuit in Verilog.
• README: Explanation of the circuit, its purpose, and my approach.
• Simulation: Simulation results, waveforms, and test benches (if applicable).
• Reflections: Insights and lessons learned during the implementation.

Feel free to follow along, offer suggestions, or learn from my progress!

Table of Contents

• Day 1: Half Adder & Full Adder
• Day 2: Ripple Carry Adder
• Day 3: Code Conversion(Gray & Binary)
• Day 4: Multiplexers
• Day 5: Demultiplexers
• Day 6: Encoders
• Day 7: Decoders
• Day 8: Latches
• Day 9: Flip-flops
• Day 10: Comparators
• Day 11: Shift Registers (1)
• Day 12: Shift Registers (2)
• Day 13: Counters
• Day 14: MOD-N Counter
• Day 15: Gray Counter
• Day 16: Booth Multiplier
• Day 17: 1-bit RAM cell
• Day 18: 4-Bit & 8-Bit RAM
• Day 19: 1,4,8-Bit ROM
• Day 20: 8-Bit ALU
• Day 21: 1101 Moore Sequence Detector
• Day 22: 1010 Mealy Sequence Detector
• Day 23: PWM (Pulse Width Modulation) generator
• Day 24: Fixed Priority Arbiter
• Day 25: Round-Robin Arbiter
• Day 26: Pseudorandom number generator
• Day 27: Frequency Divider by Even Numbers
• Day 28: Traffic Light Controller
• Day 29: Elevator Controller
• Day 30: Factorial

Let's Connect

I'd love to share my journey with you and connect with fellow Verilog enthusiasts:

• Follow me on GitHub to stay updated.
• Connect on LinkedIn for more discussions.
• Reach out via email at [email protected].

Stay Tuned

Join me as I explore the world of Verilog programming and digital circuits over the next 30 days. Let's explore, create, and learn together!

Happy Verilog coding! 💻