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Verilog to Routing -- Open Source CAD Flow for FPGA Research

Home Page: https://verilogtorouting.org

License: Other

Shell 0.69% JavaScript 0.28% Ruby 0.01% C++ 68.11% Python 4.45% Perl 0.37% C 2.22% Tcl 0.11% VHDL 0.01% Verilog 22.17% CSS 0.01% TeX 0.58% Pawn 0.01% SystemVerilog 0.33% Nix 0.01% OpenSCAD 0.01% Makefile 0.50% Cap'n Proto 0.02% HTML 0.09% CMake 0.03%

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