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License: ISC License
WebAssembly-based Yosys distribution for Amaranth HDL
License: ISC License
Numerous issues are hit when building on MacOS (tested on Montaray and Ventura):
Hi,
I am trying to use YoWASP with nmigen on an Intel Mac (on Catalina), but it seems that it is not detected by nmigen. pip freeze
inside my virtualenv looks like this:
appdirs==1.4.4
bitarray==2.3.4
click==8.0.2
Jinja2==3.0.2
MarkupSafe==2.0.1
nmigen==0.2
nmigen-boards==0.0
nmigen-soc==0.0
nmigen-stdio==0.0
nmigen-tool==0.0.1
nmigen-yosys==0.9.post3746.dev34
pyvcd==0.1.7
six==1.16.0
wasmtime==0.30.0
yowasp-nextpnr-ecp5==0.0.post3849.dev224
yowasp-nextpnr-ecp5-all==0.0.post3849.dev224
yowasp-nextpnr-ice40==0.0.post3849.dev224
yowasp-nextpnr-ice40-all==0.0.post3849.dev224
yowasp-yosys==0.9.post5623.dev231
When I try to run the 01_blinky.py
example, I get the following traceback:
Traceback (most recent call last):
File "/Users/jeremy/Seafile/misc_projects/nmigen_playing/main.py", line 21, in <module>
platform.build(Blinky(), do_program=False)
File "/Users/jeremy/Seafile/misc_projects/nmigen_playing/venv/lib/python3.9/site-packages/nmigen/build/plat.py", line 71, in build
require_tool(tool)
File "/Users/jeremy/Seafile/misc_projects/nmigen_playing/venv/lib/python3.9/site-packages/nmigen/_toolchain.py", line 33, in require_tool
raise ToolNotFound("Could not find required tool {} in PATH. Place "
nmigen._toolchain.ToolNotFound: Could not find required tool yosys in PATH. Place it directly in PATH or specify path explicitly via the YOSYS environment variable
yowasp-yosys
and yowasp-nextpnr-*
are definitely on my path; yowasp-yosys --version
returns:
Yosys 0.10+12 (git sha1 356ec7bb, ccache clang 11.0.0-2~ubuntu20.04.1 -Os -flto -flto)
Do I need to specifically force the use of YoWASP using the environment variables mentioned in the traceback?
As spotted in CI run https://github.com/amaranth-lang/amaranth-yosys/actions/runs/3269254179
upload_wheelsNode.js 12 actions are deprecated. For more information see: https://github.blog/changelog/2022-09-22-github-actions-all-actions-will-begin-running-on-node16-instead-of-node12/. Please update the following actions to use Node.js 16: actions/download-artifact
Node.js 12 actions are deprecated. For more information see: https://github.blog/changelog/2022-09-22-github-actions-all-actions-will-begin-running-on-node16-instead-of-node12/. Please update the following actions to use Node.js 16: actions/checkout, actions/setup-python, actions/cache, actions/upload-artifact, actions/cache, actions/setup-python, actions/checkout
upload_wheels
Node.js 12 actions are deprecated. For more information see: https://github.blog/changelog/2022-09-22-github-actions-all-actions-will-begin-running-on-node16-instead-of-node12/. Please update the following actions to use Node.js 16: actions/download-artifact
same as YoWASP/yosys#22
README states:
This build is aggressively optimized for binary size and startup latency, and only includes features required by Amaranth's Verilog and CXXRTL backends; it is not useful for any other purpose.
No qualms here, it's amaranth-yosys
. But, I've noticed running opt
on a design before write_cxxrtl
can (at least) speed up a low-to-moderate complexity design (barebones RV32 core) by 1.5x Hz, compiling everything with -O3
in both cases.
It's not a big deal since I can just use system Yosys, but I thought I'd bring it up and see what you thought. There's no way this would be exposed as-is (and so would be a waste except for people calling Amaranth's Yosys directly like me), but e.g. maybe one day amaranth.cli
would support enabling optimizations.
Noting here that plenty of opt
passes don't run because we don't run proc
, and running proc; opt
is worse than doing nothing, presumably because CXXRTL's own proc pass does a much better job at this.
(this unearthed when a CI build failed since I deliberately didn't install Yosys for a "units test only" job.)
As spotted in https://github.com/amaranth-lang/amaranth-yosys/actions/runs/3269254179
upload_wheels: # >> PyPA publish to PyPI GHA: UNSUPPORTED GITHUB ACTION VERSION <<#L1
You are using "pypa/gh-action-pypi-publish@master". The "master" branch of this project has been sunset and will not receive any updates, not even security bug fixes. Please, make sure to use a supported version. If you want to pin to v1 major version, use "pypa/gh-action-pypi-publish@release/v1". If you feel adventurous, you may opt to use use "pypa/gh-action-pypi-publish@unstable/v1" instead. A more general recommendation is to pin to exact tags or commit shas.
Hello All:
trying to compile amaranth-yosys, not sure if it's a yosys issue or this repo problem.
Looks like it dies on the wasm-ld linker.
Any advice would be great! Thanks
Build environment: Ubuntu 20.04 X86.
Error output, below
Makefile.conf] ENABLE_PROTOBUF := 0
[Makefile.conf] ENABLE_ZLIB := 0
[Makefile.conf]
[Makefile.conf] CXXFLAGS += -flto
[Makefile.conf] LDFLAGS += -flto -Wl,--strip-all
mkdir -p kernel/
ccache clang -o kernel/register.o -c -target wasm32-wasi --sysroot /home/mikek/Documents/Cyclone_5/DECA_Board/amaranth-yosys/wasi-sdk-11.0/share/wasi-sysroot -std=c++11 -Os -flto -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -I//include -flto -DYOSYS_DISABLE_SPAWN kernel/register.cc
mkdir -p frontends/verilog/
ccache clang -o frontends/verilog/preproc_stub.o -c -target wasm32-wasi --sysroot /home/mikek/Documents/Cyclone_5/DECA_Board/amaranth-yosys/wasi-sdk-11.0/share/wasi-sysroot -std=c++11 -Os -flto -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -I//include -flto -DYOSYS_DISABLE_SPAWN frontends/verilog/preproc_stub.cc
mkdir -p passes/cmds/
ccache clang -o passes/cmds/design_stub.o -c -target wasm32-wasi --sysroot /home/mikek/Documents/Cyclone_5/DECA_Board/amaranth-yosys/wasi-sdk-11.0/share/wasi-sysroot -std=c++11 -Os -flto -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -I//include -flto -DYOSYS_DISABLE_SPAWN passes/cmds/design_stub.cc
clang++ -o yosys.wasm -target wasm32-wasi --sysroot /home/mikek/Documents/Cyclone_5/DECA_Board/amaranth-yosys/wasi-sdk-11.0/share/wasi-sysroot -Wl,-z,stack-size=1048576 -flto -Wl,--strip-all -flto -Wl,--strip-all kernel/version_85067f3.cc kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/mem.o kernel/yosys.o libs/bigint/BigInteger.o libs/bigint/BigUnsigned.o libs/sha1/sha1.o frontends/ast/ast.o frontends/rtlil/rtlil_parser.tab.o frontends/rtlil/rtlil_lexer.o frontends/rtlil/rtlil_frontend.o frontends/verilog/preproc_stub.o frontends/verilog/const2ast.o passes/hierarchy/hierarchy.o passes/hierarchy/uniquify.o passes/hierarchy/submod.o passes/proc/proc.o passes/proc/proc_prune.o passes/proc/proc_clean.o passes/proc/proc_rmdead.o passes/proc/proc_init.o passes/proc/proc_arst.o passes/proc/proc_memwr.o passes/proc/proc_mux.o passes/proc/proc_dlatch.o passes/proc/proc_dff.o passes/opt/opt_expr.o passes/cmds/plugin.o passes/cmds/design_stub.o passes/cmds/select.o passes/cmds/delete.o passes/memory/memory_collect.o passes/techmap/attrmap.o passes/techmap/flatten.o backends/rtlil/rtlil_backend.o backends/cxxrtl/cxxrtl_backend.o backends/verilog/verilog_backend.o -lstdc++ -lm
wasm-ld: error: backends/verilog/verilog_backend.o: undefined symbol: Yosys::FfData::FfData(Yosys::FfInitVals*, Yosys::RTLIL::Cell*)
clang-10: error: linker command failed with exit code 1 (use -v to see invocation)
make: *** [Makefile:700: yosys.wasm] Error 1
make: Leaving directory '/home/mikek/Documents/Cyclone_5/DECA_Board/amaranth-yosys/yosys-src'
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