antmicro-labs / fastvdma-wrapper Goto Github PK

Recreate the test from DMAFull.scala

FastVDMA has two interrupts lines: irq_readerDone and irq_writerDone. We can wrap them using the EventManager like here.

I created the branch wishbone_connection and commited there how I understand the buses should be connected.
Also, I'm not sure how the control_bus should be implemented for easy access and debugging - I tried to create my own SoC using this wrapper, but I get error from the Vivado's placer

ERROR: [Place 30-494] The design is empty
Resolution: Check if opt_design has removed all the leaf cells of your design.  Check whether you have instantiated and connected all of the top level ports.

Vivado is also complaining that the designs WishboneCSR and DMATop have unconnected ports.
Should I connect them differently? How?
AFAIK, the *stall signals aren't connected to anything when using the WishboneClassicReader/Writer in the original fastvdma, so I connected them to the constant 0.