antmicro-labs / video-processing Goto Github PK

I have added links to useful resources to the project Wiki. Please, have a look at this.

Based on the migen tutorial I already know that the "yield" keyword used on its own begins the next clock cycle. I'm not sure tho what its purpose is while referring to user-defined signals in modules. Example in the picture below. Could you please clarify this?

For preparing the needed binaries, use the Enclustra Build Environment. All the information should be available in the project documentation.

Get with WishBone bus, AXI bus, and place it in project.
Add software block between AXI and wishbone to communicate those two buses.
Take data, address and transactions into consideration.

To output HDMI stream you need to add a video IP core. In LiteX based systems - LiteVideo is the obvious choice https://github.com/enjoy-digital/litevideo

You can find an example in the netv2 project https://github.com/antmicro/netv2

LiteX normally uses Wishbone bus. The CPU system in Zynq uses AXI to communicate them both you need to add an Wishbone <-> AXI bridge to the design.

This one is quite simple and can be easily integrated: https://github.com/wallento/wb2axi/blob/master/src/wb2axi.sv

Build new design for ARTY board, run design in simulation.
Build design for zynq board with copied def arty and defined ports and interfaces.
Take names for ports and devices from vivado.

Platform defining:
Take LiteX -> Read run instruction -> build ready-design for Arty board (using arty.py) -> try to build it on Zynq -> copy Arty definition and arrange it for our board* (don't forget about UART definition!)

Define parts in Platform() class + Remove self.toolchain + comment SDRAM and Ethernet

• Mars ZX2-20-21-* - last from 4 in Enclustra docs

Links:
https://github.com/antmicro/zynq-video-board/blob/master/Documentation/Zynq-Video-Board-v1.2-Pinouts.pdf
https://download.enclustra.com/

Chciałbym zapytać kiedy udostępnione zostaną jakieś materiały (dokumentacja, soft z którym możemy się początkowo zapoznać itp.). Tak na dobrą sprawę też ciężko jest chwilowo określić cele do issues'ów, ponieważ brakuje nam fizycznych materiałów do ich sprecyzowania.

Perform simple video processing block, for example colors invert (RGB->BRG), conversion from one standard to another one (YUV->RGB). Everything has to be tested!

In simulations include the case when valid ready isn't 1.