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SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API.

License: Apache License 2.0

ANTLR 2.54% C++ 54.35% SystemVerilog 28.36% Tcl 1.43% Python 2.36% C 0.06% Makefile 0.11% Forth 0.01% Verilog 8.78% V 0.02% CMake 1.07% Slash 0.78% Shell 0.03% SWIG 0.01% Nix 0.02% Cap'n Proto 0.11%

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