Literal Operations |
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number = kkkk kkkk |
MOVLW |
move a number to w |
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11 0000 kkkk kkkk |
ADDLW |
kkkk_kkkk + w |
w |
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11 1110 kkkk kkkk |
IORLW |
kkkk_kkkk | w |
w |
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11 1000 kkkk kkkk |
ANDLW |
kkkk_kkkk & w |
w |
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11 1001 kkkk kkkk |
SUBLW |
kkkk_kkkk - w |
w |
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11 1100 kkkk kkkk |
XORLW |
kkkk_kkkk ^ w (XOR) |
w |
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11 1010 kkkk kkkk |
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. |
Register Operations |
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d=ir_out[7] |
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ADDWF |
w + fff_ffff (register file address 0x00~0x7f) |
d==0 |
w |
00 0111 dfff ffff |
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d==1 |
register |
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ANDWF |
w & fff_ffff |
d==0 |
w |
00 0101 dfff ffff |
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d==1 |
register |
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CLRF |
clear fff_ffff to 0 |
register |
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00 0001 1fff ffff |
CLRW |
clear w to 0 |
w |
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00 0001 0000 00xx (x:Don't care) |
COMF |
not fff_ffff |
d==0 |
w |
00 1001 dfff ffff |
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d==1 |
register |
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DECF |
fff_ffff - 1 |
d==0 |
w |
00 0011 dfff ffff |
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d==1 |
register |
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INCF |
fff_ffff + 1 |
d==0 |
w |
00 1010 dfff ffff |
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d==1 |
register |
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IORWF |
w | fff_ffff |
d==0 |
w |
00 0100 dfff ffff |
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d==1 |
register |
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MOVF |
move fff_ffff to |
d==0 |
w |
00 1000 dfff ffff |
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d==1 |
register |
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SUBWF |
fff_ffff - w |
d==0 |
w |
00 0010 dfff ffff |
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d==1 |
register |
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XORWF |
fff_ffff ^ w |
d==0 |
w |
00 0110 dfff ffff |
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d==1 |
register |
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addr_port_b = (ir_out[6:0]==7'h0d) |
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MOVWF |
move w to |
addr_port_b == 0 |
register |
00 0000 1fff ffff |
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addr_port_b == 1 |
port_b |
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sel_bit=ir_out[9:7] |
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BCF |
bit clear f (set sel_bit to 0) |
register |
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01 00bb bfff ffff |
BSF |
bit set f (set sel_bit to 1) |
register |
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01 01bb bfff ffff |
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. |
Skip Operations |
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BTFSC |
bit Test f, Skip if Clear (sel_bit==0) |
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01 10bb bfff ffff |
BTFSS |
bit Test f, Skip if Set (sel_bit==1) |
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01 11bb bfff ffff |
DECFSZ |
Decrement f, Skip if 0 |
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00 1011 dfff ffff |
INCFSZ |
Increment f, Skip if 0 |
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00 1111 dfff ffff |
PORTBCSZ |
skip 2 instructions if((port_b_out & port_c_out) == 0) |
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00 0000 0000 0011 |
INCFEQCSZ |
Increment register(ir_out[7:0]), Skip if it equals port_c_out |
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11 0100 kkkk kkkk |
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. |
Rotate Operations |
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ASRF |
remain sign bit and right shift fff_ffff |
d==0 |
w |
11 0111 dfff ffff |
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=>{ mux1_out[7],mux1_out[7:1] } |
d==1 |
register |
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LSLF |
left shift fff_ffff |
d==0 |
w |
11 0101 dfff ffff |
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=>{ mux1_out[6:0], 1'b0 } |
d==1 |
register |
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LSRF |
right shift fff_ffff |
d==0 |
w |
11 0110 dfff ffff |
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=>{ 1'b0, mux1_out[7:1] } |
d==1 |
register |
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RLF |
rotate left fff_ffff |
d==0 |
w |
00 1101 dfff ffff |
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=>{ mux1_out[6:0], mux1_out[7] } |
d==1 |
register |
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RRF |
rotate right fff_ffff |
d==0 |
w |
00 1100 dfff ffff |
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=>{ mux1_out[0], mux1_out[7:1] } |
d==1 |
register |
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SWAP |
do half swap on fff_ffff |
d==0 |
w |
00 1110 dfff ffff |
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{m7, m6,...m4, m3,...m0} => {m3,...m0, m7, m6,...m4} |
d==1 |
register |
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. |
Control Operations |
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GOTO |
PC_out = ir_out[10:0] |
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10 1fff ffff ffff |
CALL |
stack[stk_ptr + 1]=pc_q |
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10 0kkk kkkk kkkk |
RETURN |
pc_q = stack[stk_ptr] |
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00 0000 0000 1000 |
BRA |
pc_next = pc_q + {ir_out[8], ir_out[8], ir_out[8:0]} - 1 |
limit: 255 instructions backward or 256 instructions forward |
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11 001k kkkk kkkk |
BRW |
pc_next = pc_q + {3'b0, w_q} - 1 |
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00 0000 0000 1011 |
NOP |
No Operation |
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00 0000 0000 0000 |