arhamhashmi01 / rv32i-sv

This repository contain the implementation of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on System Verilog

Hi 👋, I'm Syed Arham Hashmi

A Passionate Computer Engineer

Computer Systems Engineering student passionate about technology and innovation. Proficient in programming languages like Python, Verilog,RISC-V Assembly and C++, I'm eager to contribute meaningfully to the field. Let's connect and explore opportunities together!

• 🌱 I’m currently learning VLSI | ASIC Design | FPGAs

• 💬 Ask me about C++ | Verilog | Python | RISC-V Assembly

• 👯 I’m looking to collaborate on RISC-V

• 👨‍💻 All of my projects are available at https://github.com/arhamhashmi01

• 📫 How to reach me [email protected]

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