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Avnet Board Definition Files
TCL get_board_parts command in Vivado 2021.2.1 shows "em.avnet.com:minized:part0:1.2 " but "avnet.com:minized:part0:1.3" (i.e. no "em" prefix on vendor).
Generating a system in Vitis Model Composer using the board file is not possible and produces the following error when Minized is selected as the board:
ERROR: An error occurred when creating the Vivado project.
ERROR: [Board 49-71] The board_part definition was not found for em.avnet.com:minized:part0:1.3. The project's board_part property was not set, but the project's part property was set to xc7z007sclg225-1. Valid board_part values can be retrieved with the 'get_board_parts' Tcl command. Check if board.repoPaths parameter is set and the board_part is installed from the tcl app store.
Changing the board.xml file for the 1.3 version so that vendor is "em.avnet.com" rather than "avnet.com" fixes the issue and Model Composer system generation is possible:
<board schema_version="2.2" vendor="em.avnet.com" ... >
I have made the change locally but would be good if the repo can be updated with this change.
Hello,
I am trying to use new v2 bdfs in the Vitis chain with Vivado 2020.3 in 18.04 LTD, importing my work from Vivado 2018.3:
I get a device type mismatch because the pdf is specifying the -i not the -e in previous files, I
hacked that but there is still the complaint about locked ip and bus width changes with respect
to v2 1.0 ..
Any guidance would be greatly appreciated, thank you
Hi, looking at this repo I'm trying to understand why picozed has a bdf with an fmc carrier while a microzed - which also has an FMC carrier board is not included?
To Whom It May Concern:
There no longer appears to be an updated ultrazed_7ev_som BDF anymore. I was able to locate one, but it has been moved to the deprecated directory. Shouldn't there be a current ultrazed_7ev_som BDF?
Best Regards,
Joseph
Hello,
I noticed that the speed grade among Ultra96v2 BDF revision 1.1 changed from "e" to "i" w.r.t. revision 1.0.
Is this correct?
Thank you in advance
Regards
I recently completed a new board definition file for a Xilinx Vivado project (2019, 2020 editions) for a Seeed Studio Accelerator FPGA board - and I learnt a lot of tips/tricks to creating Xilinx board files. I also purchased a MiniZed board to create a whole testbed system last year, and just got around to working in setting it up - so my information on it may be out of date. Is the BDF for the MiniZed complete? I did not see a definition / component / connection spec for the PMOD #1 and PMOD #2 connectors? If these are missing, is there a timeline for an updated MiniZed BDF?
I can help and contribute a modified BDF with the missing pieces - to the best of my ability - but to start, I would like to know the formal port names and connectors per a schematic or spec guide?
After copying the board definitions (as explained in the docs) the boards do not show up under the boards in Vivado 2020.3
It worked with Vivado 2020.2
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