bit-hack / riscv-vm

A Small RISC-V Virtual Machine

RISC-V Virtual Machine

This is a RISCV-V Virtual Machine and instruction set emulator implementing a 32 bit RISCV-V processor model. I started this project as a learning exercise to get more familiar with the RISC-V eco system and have increased the scope of the project as it matures. The project itself is still very much in the early stages however.

Features:

• Support for RV32I and RV32M
• Partial support for RV32F and RV32A
• Syscall emulation and host passthrough
• Emulation using Dynamic Binary Translation
• It can run Doom, Quake and SmallPT

There are broadly two elements to this project:

• An ISA emulator core written in C which presents a low level API for interfacing.
• The VM frontend written in C++ which interfaces the ISA emulator core with the host computer.

Note: The Binary Translation emulator is currently only available when building for x64 Windows. This is due to the generated code being tailored to that ABI, however in time Linux support for the code generator will follow.

See news for a development log and updates.

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Build Status

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Build requirements

• C++ 14 compatible compiler (VisualStudio 15+, GCC 4.9+)
• CMake 3.0 or above
• SDL1.2 (if you want video support)

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Compiling the project

mkdir build
cd build
cmake ..
make

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Executing a basic program

A simple RISC-V program (i.e. main.c) can be compiled and executed as follows:

riscv64-unknown-elf-gcc -march=rv32im -mabi=ilp32 main.c
riscv_vm a.out

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Testing

Please note that while the riscv-vm simulator is provided under the MIT license, any of the materials in the tests folder may not be. These tests were taken from a wide range of places to give the project a reasonable test coverage. If you are the author of any of these tests and are unhappy with its inclusion here then please get in touch and I will remove it from the project and its git history.

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Notes

• Written referencing the 20191214-draft Volume I: Unprivileged ISA document
• Complete RV32G compliance is the end goal
• Testing is done currently using a private fork of the compliance test suite
  • As the project develops testing will become a key focus
• It is enough that it can run doom, see the README

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Newlib support

There is rudimentary support for target programs that make use of the newlib library. Currently a number of syscalls have been implemented via the ecall instruction. This is just enough to run a number of simpler programs and do some basic file io operations.

Try the following example program:

#include <stdio.h>

int main(int argc, const char **args) {
  printf("Hello World!\n");
  return 0;
}

Spoiler:

Hello World!

riscv-vm's Issues

Error on Make

I get a few errors when I call make:

Building CXX object CMakeFiles/riscv_vm.dir/riscv_vm/syscall.cpp.o syscall.cpp: In function ‘void syscall_write(riscv_t*)’:

syscall.cpp:97:29: error: ‘alloca’ was not declared in this scope 97 | uint8_t *temp = (uint8_t*)alloca(count);

syscall.cpp:231:29: error: ‘alloca’ was not declared in this scope 231 | uint8_t *temp = (uint8_t*)alloca(count); | ^~~~~~ make[2]: *** [CMakeFiles/riscv_vm.dir/build.make:104: CMakeFiles/riscv_vm.dir/riscv_vm/syscall.cpp.o] Error 1 make[1]: *** [CMakeFiles/Makefile2:196: CMakeFiles/riscv_vm.dir/all] Error 2 make: *** [Makefile:91: all] Error 2

How negative value in a registers are handled?

Could @bit-hack please explain how negative values in registers are handled?
For example say ADDI r5, r0, 100 and say r0 has value -100 (in 2's complement)
will following give correct answer ?

82    case 0: // ADDI    Aidan Dodds, 20/09/20 16:10 • tidy and fix SRAI bug                                                                                                                                      
  1     rv->X[rd] = (int32_t)(rv->X[rs1]) + imm;                                                                                                                                                                  
  2     break;          

because X stores unsigned integer AFAIU then above seems not handled correctly.

Understand how ELF is used within riscv-vm.

1. How to locate the start of actual instruction from the .text section and how to figure out where to stop?
2. I see that your implementation reads all PT_LOAD sections into a buffer but then how to distinguish between .text (.rodata) and .data ?

#include <alloca.h> is missing