bobmshannon / simple-32bit-alu-design

A simple, working, 32-bit ALU design.

Simple-32bit-ALU-Design

An implementation of a simple 32 bit ALU using verilog with working zero delay simulations.

To run:

$ verilog alu_zero.v

$ ./a.out

simple-32bit-alu-design's Issues

Fix schematic for SLT

Need logic to select MSB (which will be 1 or 0 depending on of X-Y is negative), and put that bit into f[0]. f[31:1] should then be filled with zeros.

Fix zero output

Zero output needs to be asserted when F=0. Otherwise deassert.