briansune / tang-mega-138k-pro-ddr3

Tang Mega-138K Pro-DDR3

TangMega-138KPro-DDR3

If this project is constructive, welcome to donate a drink to PayPal.

EDA Version 19.9.01 !!!!!!

This example is intended on TangMega 138KPro Modified DDR3 Board and Default Configuration Board

Aim: The example is continuously write and read back to check sanity of handshaking between DDR IP controller and custom FSM.

The debug methodology is address / 8 = write/read content app_data := {32{addr/8}}

How to capture? Setup the trigger address, and reset the FPGA board via the push button!

GAO Capture

Explain of MT41J128M16-125:K and IP configuration

DDR Datasheet

GAO Capture

Explain of H5TQ4G63EFR-RDC and IP configuration

DDR Datasheet

Because the suffix of the DDR3 is RD and C with support of previous DDR speed.

For tCKE the datasheet does not clearly mention any data, from general rule of DDR3 mostly about 3N of tCK.