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View Code? Open in Web Editor NEWA 16-bit, 5-stage RISC processor. RTL description in Verilog. Includes assembler, simulator, and example programs.
License: GNU General Public License v3.0
A 16-bit, 5-stage RISC processor. RTL description in Verilog. Includes assembler, simulator, and example programs.
License: GNU General Public License v3.0
Need scripts that automatically run test programs, compare their output against golden output, and report back.
Consider removing src3 from data path. It seems unnecessary.
Need more extensive testing. Maybe factorial calculation ...
Program a standalone assembler (maybe in Python).
Do we really need the option to negate both src1 and src2? We should try to make due with the option to negate src2 only. Branch instructions and the sub instruction have to be re-checked after making this change.
Nice little demo using a sliding convolutional filter.
Rename out_act_write_res_to_reg (rtl/decoder.v) to something more meaningful.
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