captaindane / swt16 Goto Github PK
View Code? Open in Web Editor NEWA 16-bit, 5-stage RISC processor. RTL description in Verilog. Includes assembler, simulator, and example programs.
License: GNU General Public License v3.0
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poberherrswt16's Issues
Introduce automated testing.
Need scripts that automatically run test programs, compare their output against golden output, and report back.
Remove src3
Consider removing src3 from data path. It seems unnecessary.
Add more sophisticated test programs.
Need more extensive testing. Maybe factorial calculation ...
Implement pipeline stalling for cases where bypassing is not feasible (mem access)
Introduce Assembler
Program a standalone assembler (maybe in Python).
JAL and JALR don't write correct incremented pc to register
Implement operand bypassing / forwarding
Evaluate src1 and src2 negation in exec.v
Do we really need the option to negate both src1 and src2? We should try to make due with the option to negate src2 only. Branch instructions and the sub instruction have to be re-checked after making this change.
Add image processing test application
Nice little demo using a sliding convolutional filter.
Include assembler into automatic test flow
Automated test script should rebuild simulator if needed
Rename out_act_write_res_to_reg
Rename out_act_write_res_to_reg (rtl/decoder.v) to something more meaningful.
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