Comments (1)
@hstarmans yes the SDRAM controller in rhea is not complete - I must have made a mistake merging some of it in to the main branch (should only be available as WIP on the sdram branch)? It is essentially a port of @udara28's version but using some of the framework in rhea.
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Related Issues (20)
- Outside Interfacing HOT 1
- Add a digilent basys3 board definition
- Change GPIO pin assignments to Peripheral based devices vs FPGA based. HOT 6
- travis-ci build matrix
- Would be nice if Clock() type exposed 'clock ticks' to 'simulation ticks' ratio. HOT 4
- vga: use the timing parameter class vs. function
- Vivido 2016.2 and ISE 14.7 can't process generated .tcl files with absolute paths or spaces on windows 10 HOT 6
- It would be nice if clocks could generate architecture specific clock tiles as needed. HOT 1
- [bug] device_clock_mgmt_prim() will not convert due to using unsupported myhdl features. HOT 7
- [enhancement] create a skipif synthesis tool not available
- Would be nice if flow.run() provided board information to the top module for things like ClockManagement HOT 2
- ClockManagement's clocks[n] is not driven on Xilinx parts - though ClockManagement's clocksout(n) is. HOT 2
- ClockManagement's 'enable' parameter is not implemented on Xilinx parts HOT 2
- Symbol 'MMCME2_BASE' is not supported in target 'spartan6'. HOT 3
- Support Diligent Adept's 'djtgcfg' utility for flow.program() on applicable Diligent boards HOT 1
- instructions: xula_blinky_host.py on raspberry pi 3B [solved] HOT 7
- [enhancement] Provide board definition and blinky example for Red Pitaya HOT 1
- spi_slave_fifo_async
- register file example
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