chappie19 / serdes

Verilog RTL Design

Serializer-Deserializer

A simple implementation of a SerDes module, typically used in high-speed communication protocols like PCIe, DisplayPort, Gigabit Ethernet, USB etc.

• RTL Design has basic modules like Latches, Encoder, Decoder, Shift Registers -> Parallel-In-Serial-Out, Serial-In-Parallel-Out

• Serializer latches onto 8-bit Parallel data input, encodes to 10-bit, and converts to Serial bits

• Deserializer converts incoming Serial bits to Parallel data using 10-bit latches, decodes and outputs back as 8-bit

• Followed specifications to implement 3b/4b & 5b/6b encoding schemes and maintain a DC-balance data stream