Comments (6)
I've checked the tests you listed and I discovered the following things:
12.7.5
fails because it is missing a;
afterwhile(...)
, soon this will be fixed by #1105.6.1
seems to fail because of missing;
and it also fails when tested manually usingtree-sitter-cli
with error5.6.1--escaped-identifiers.sv 1 ms (MISSING ";" [8, 19] - [8, 19])
- remaining tests from the
generic
subdirectory also seem to fail both intree-sitter-cli
with errors like(MISSING simple_identifier [7, 9] - [7, 9])
and in our test suite
Are you sure that those tests passed on your side?
In general test is marked as failed in tree-sitter-verilog
runner when any node has the has_error property set to True
and this has been the case in all mentioned tests.
from sv-tests.
5.6.1
seems to fail because of missing;
and it also fails when tested manually usingtree-sitter-cli
with error5.6.1--escaped-identifiers.sv 1 ms (MISSING ";" [8, 19] - [8, 19])
Why is that error not seen in the report? This is a bug in the python runner and should be fixed in my opinion, otherwise the logs are pretty useless
from sv-tests.
Currently logs only show the part of the node hierarchy that has the has_error
flag set, ie. in case of 5.6.1
:
...
(0, 0) source_file
(6, 0) module_declaration
(8, 2) module_or_generate_item
(8, 2) data_declaration
(8, 19) ;
...
and for a run that succeeded the log should be empty.
Maybe the runner can be enhanced to directly state at the end of the log that the error is in this particular line and what kind of error it is
from sv-tests.
@piotr-binkowski you are right. Cases are failing. It just the log was confusing.
from sv-tests.
I have released https://github.com/tree-sitter/tree-sitter-verilog v0.18.0 here that fixes these and many other issues. Please upgrade.
Verilog grammar for tree-sitter. Contribute to tree-sitter/tree-sitter-verilog development by creating an account on GitHub.
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The misleading messages have been improved in #200 so I guess this can be closed now.
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Related Issues (20)
- Include column sorting option in URL
- Create anchor for sub-tables
- a way to make the Pyhon dependencies more hermetic ?
- Use standard naming of some binaries (yosys-uhdm, zachjs-sv2v)
- Need more tests HOT 1
- ariane file set is out of sync with ariane core HOT 1
- table headers obstruct log-file view
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- scr1: missing include directory ? HOT 2
- tree-sitter-verilog: essentially all tests fail with "Incompatible Language version" HOT 1
- 11.4.8: continuous assignments races with initial block HOT 6
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- UVM-related tests come with undefined package's import HOT 1
- Ariane core test is broken
- RgGen core is broken HOT 1
- VeeR EL2 core is broken HOT 3
- Adding opl3_fpga to cores
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