Comments (3)
I'm quite fond of the idea of a monadic interface, at least in principle. Here is my attempt: https://git.smart-cactus.org/ben/clash-play/blob/master/TestM.hs.
from clash-prelude.
Just to supply some inspiration, here is an example of the test bench that I would like to be able to write,
-- | A test plan for a component accepting inputs of type @i@ and outputs of type @o@
data TestM clk i o a
-- | Feed the DUT an input, return the output that it produces.
tick :: i -> TestM clk i o o
-- | Feed the DUT the given input until it produces an output that satisfies
-- the given predicate.
tickUntil :: i -> (o -> Bool) -> TestM clk i o o
-- | A simple assertion
assert :: Bool -> String -> TestM clk i o ()
testIt :: TestM System (AxiIn 13 32) (AxiOut 13 32) ()
testIt = do
tick defAxiIn -- feed the DUT with an input
tickUntil
(defAxiIn & axiReadIn %~
( (arvalid .~ True)
. (arid .~ TransId 1)
. (araddr .~ 32)
. (arlen .~ 0)
. (arsize .~ BurstSize 4)
. (arburst .~ BurstIncr)))
(view $ axiReadOut . arready)
o <- tickUntil defAxiIn (view $ axiReadOut . rvalid)
assertEqual "Data" 10 (o ^. axiReadOut . rdata)
Unfortunately, it's not at all clear how to implement such an interface in a safe way. You can approximate the desired semantics with some clever knot tying, but it's hard to preserve the property that tick
gives you the output from cycle n
on the n
th invocation.
from clash-prelude.
How about something like this?
data Test i o = Tick i | TickUntil i (o -> Bool)
testMachineS plan curOutput = case plan of
[] -> error "finished"
Tick _:rest -> rest
TickUntil _ f:rest -> if f curOutput then rest else plan
testMachineO plan = case plan of
[] -> error "finished"
Tick i:_ -> i
TickUntil i _:_ -> i
testIt
:: (Signal domain i -> Signal domain o)
-- ^ Function to test
-> [Test i o]
-- ^ Plan
-> [o]
testIt dut plan = sample o
where
o = dut inp
inp = moore testMachineS testMachineO plan o
from clash-prelude.
Related Issues (20)
- asyncRam' :: Enum addr => SClock wclk -> SClock rclk -> SNat n -> Signal' wclk (Maybe (addr, a)) -> Signal' rclk (addr -> a) HOT 8
- Changing `()`'s `Bundle` instance to be like the other tuple instances? HOT 2
- Should signal be that general? HOT 1
- Case-expression in BitVector's signExtend should be exhaustive
- Mark CLaSH.Prelude.Synchronizer safe
- stepLock eats my tuple data HOT 1
- `regEn#` fails to converge in sim when enable depends on previous output
- No enable signal for function `window` HOT 2
- window could have simpler signature HOT 1
- abs of SFixed does not saturate. HOT 3
- Eventually remove lambdaDrop HOT 1
- DDR primitive documentation
- Remove uses of `data-default` HOT 1
- Rename `satMin` to `satSub` HOT 3
- Possible regression with the Traversable instance of Vec HOT 2
- clash-prelude-0.11.2 fails to build with ghc-typelits-natnormalise-0.5.5 HOT 1
- unsafeSNat doesn't synthesise HOT 1
- `simulate` et al. raise a spurious/misleading exception when inputs are exhausted
- GHC Version in README.md HOT 1
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from clash-prelude.