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DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art DDR4 modules of different form factors. Five prototypes are available on different FPGA boards. Described in our preprint: https://arxiv.org/pdf/2211.05838.pdf

License: MIT License

TeX 0.03% Shell 2.67% Tcl 1.19% Pascal 0.01% Verilog 8.59% VHDL 63.02% SystemVerilog 16.84% V 3.05% C++ 2.45% Stata 0.86% Forth 0.29% C 0.89% Makefile 0.03% Lex 0.01% Yacc 0.02% Python 0.06% Csound 0.01%
dram fpga rowhammer testing

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dram-bender's Issues

About DFI to Xilinx Phy Interface

Hello, I read in your paper "We issue DRAM commands to the Xilinx DDR3/4 PHY IP [370] over a low-level DFI interface." Then because the Xilinx DDR PHY interface does not support the DFI protocol, when using a controller with the DFI protocol, an adapter is needed to convert the DFI signal to the Xilinx DDR PHY signal, similar to converting dfi_cas_n---->mc_CAS_n, etc. Then I saw ddr4_adapter.v in your project. If I want to further implement my needs, which files should I refer to?

XDMA error: the kernel is correct but the device is not detected.

Hi everyone,
We met a problem about the XDMA when we followed the tutorial:https://github.com/CMU-SAFARI/DRAM-Bender. The error report is that: the kernel is correct but the device is not detected.
The environment we tried is shown as following:
Vivado 2020.1, 2020.2, and 2022.2
Ubuntu 20.04 & 18.04(kernel 5.15 and 5.14)
XRT for Ubuntu 20.04https://www.xilinx.com/products/boards-and-kits/alveo/u200.html#gettingStarted
Xilinx Runtime
Deployment Target Platform
Development Target Platform
XRT for Ubuntu 18.04https://www.xilinx.com/products/boards-and-kits/alveo/u200.html#gettingStarted
Xilinx Runtime
Deployment Target Platform
Development Target Platform
XRT Ubuntu 18.04 GitHub Installation https://xilinx.github.io/XRT/master/html/install.html
Alveo U200 (2020.1 XDMA https://www.xilinx.com/products/boards-and-kits/alveo/package-files-archive/u200-2020-1.html
https://www.omgubuntu.co.uk/2020/08/ubuntu-18-04-5-lts-released-with-linux-kernel-5-4

We also watched the video about DRAM-Bender: https://www.youtube.com/watch?v=FklVEsfdZCI

XDMA Driver Configuration, Possible issue

When following the Row Hammer example provided at this link on youtube
https://www.youtube.com/watch?v=FklVEsfdZCI

we are running into an issue where the number of bit flips does not match the values it should be. For example when we do sudo ./ps10, it gives the same value as sudo ./ps100, sudo ./ps1000, sudo ./ps10000 etc.

we are using the xdma driver that came with the github repo but when we use xilinx's latest XDMA driver we get this issue.

1017: ADDI r10 r10 1
1018: BL PC:627 r10 r11 (TARGET LABEL: READ_BEGIN)
1019: END
ps: ../../api/board.cpp:128: int BoardInterface::xdma_recv(void*, uint): Assertion `count <= size' failed.
Aborted

can you let us know what might be wrong?

I have also attached out code file to this error and also a photo of out vivado program output
DRAMBENDERCODE.txt

ProgramOutput.txt

DRAM BENDER TUTORIAL ISSUES

Hello we are trying to figure out how to use the dram bender tutorial from the youtube video and are running into an issue with the number of bit flips being very high than expected? we have even tried to print the values of the rows and still are seeing a data pattern miss match. WOuld someone be able to take a look at our solution and maybe see what could be wrong.

#include "instruction.h"
#include "prog.h"
#include "platform.h"
//#include
#include
#include
#include
using namespace std;

int main(int argc, char * argv[])
{

int hammer_count = atoi(argv[1]); // arguement the program takes from the command line aka when you do .ps 10 10 is the hammer count which indicates the number of times the row will be activated 

SoftMCPlatform platform; //sends and recieves info from the board

platform.init();

platform.reset_fpga(); // sets a reset signal to the fpga we send it everytime to get the state to a meaningful start

Program p; //program object

const int ROW_ADDRESS_R = 3;
const int BANK_ADDRESS_R = 4;
const int COLUMN_ADDRESS_R = 5;

p.add_inst(SMC_LI(99,ROW_ADDRESS_R)); //load immediate which initializes a register with an immeidiate value aka 999 which goes to rowaddress 3
p.add_inst(SMC_LI(0, BANK_ADDRESS_R));
p.add_inst(SMC_LI(0, COLUMN_ADDRESS_R));


const int DATA_PATTERN_R = 6; // dram data register to initialize rows with data 32 bit x 32 bit but with one insruction we can only modify 32 bits at a time
const int DATA_PATTERN_INV_R = 7;

p.add_inst(SMC_LI(0xFFFFFFFF, DATA_PATTERN_R));
p.add_inst(SMC_LI(0x00000000, DATA_PATTERN_INV_R));

for (int i = 0; i < 16; i++)  // this loop takes into account the 32 x 32 bit since the register is 512 bit wide 16 of these 32 bits which takes the the register identifier and loads with i aka the offset to initalize all of the rows
    p.add_inst(SMC_LDWD(DATA_PATTERN_INV_R, i));

p.add_inst(SMC_PRE(BANK_ADDRESS_R, 0, 1), SMC_NOP(), SMC_NOP(), SMC_NOP()); // this just makes sure that all of the banks are precharged reason to do this is is because the rows might be in an undifined state which is why we want to minimize that error
p.add_inst(SMC_SLEEP(10));// one dram command can execute 4 dram commands || what sleep does is does no operations for that number of fpga clock cycles aka 10 

//Write to victim row one.
p.add_inst(SMC_ACT(BANK_ADDRESS_R, 0, ROW_ADDRESS_R, 0), SMC_NOP(), SMC_NOP(), SMC_NOP());  // we activate bank 0 and row 999 
p.add_inst(SMC_SLEEP(10)); // nakul

for (int i = 0; i<128; i++) // this writes to the whole dram row that we activated 128 weite commands which takes the bank address and the column address which is a offset in the row since we initialized the data pattern with all 1's its going to write all 1's
{
    p.add_inst(SMC_WRITE(BANK_ADDRESS_R, 0, COLUMN_ADDRESS_R, 0, 0, 0), SMC_NOP(), SMC_NOP(), SMC_NOP());
    p.add_inst(SMC_ADDI(COLUMN_ADDRESS_R, 8, COLUMN_ADDRESS_R)); //incrementing the column address by 8 by because a single read or write it reaches 8 consecutive columns 512 bits to 8 columns aka 64 bits a column
}

p.add_inst(SMC_SLEEP(10)); //nakul
p.add_inst(SMC_PRE(BANK_ADDRESS_R, 0, 0), SMC_NOP(), SMC_NOP(), SMC_NOP()); // sleep just in case and then pre charge as a precaution

p.add_inst(SMC_ADDI(ROW_ADDRESS_R, 1 ,ROW_ADDRESS_R)); // increment the row address register by 1 aka the victim row and i want to initalize the agressor row
p.add_inst(SMC_LI(0, COLUMN_ADDRESS_R)); // reset column address register to 0

// load the aggressor row data pattern // load this with all 0's  to initialize the data 
for (int i = 0; i < 16; i++)
    p.add_inst(SMC_LDWD(DATA_PATTERN_INV_R, i));

// write to the aggressor row
p.add_inst(SMC_ACT(BANK_ADDRESS_R, 0, ROW_ADDRESS_R, 0), SMC_NOP(), SMC_NOP(), SMC_NOP()); // same thing as what we did above
p.add_inst(SMC_SLEEP(3));//nakul
for (int i = 0; i < 128; i++)
{
    p.add_inst(SMC_WRITE(BANK_ADDRESS_R, 0, COLUMN_ADDRESS_R, 0, 0, 0), SMC_NOP(), SMC_NOP(), SMC_NOP());
    p.add_inst(SMC_ADDI(COLUMN_ADDRESS_R, 8, COLUMN_ADDRESS_R));
}
p.add_inst(SMC_SLEEP(10));//nakul
p.add_inst(SMC_PRE(BANK_ADDRESS_R, 0, 0), SMC_NOP(), SMC_NOP(), SMC_NOP());

// //write to the second victim row
p.add_inst(SMC_LI(0, COLUMN_ADDRESS_R));

  // increment row address register by one
  p.add_inst(SMC_ADDI(ROW_ADDRESS_R, 1, ROW_ADDRESS_R));

  for (int i = 0; i < 16 ; i++){
      p.add_inst(SMC_LDWD(DATA_PATTERN_R, i));}
      //from buffer (Row 0):


  p.add_inst(SMC_ACT(BANK_ADDRESS_R, 0, ROW_ADDRESS_R, 0), SMC_NOP(), SMC_NOP(), SMC_NOP());
  p.add_inst(SMC_SLEEP(10));//nakul
  for (int i = 0; i <128 ; i++)
  {
      p.add_inst(SMC_WRITE(BANK_ADDRESS_R, 0, COLUMN_ADDRESS_R, 0, 0, 0), SMC_NOP(), SMC_NOP(), SMC_NOP());
      p.add_inst(SMC_ADDI(COLUMN_ADDRESS_R, 8, COLUMN_ADDRESS_R));
  }
 p.add_inst(SMC_SLEEP(10));//nakul
 p.add_inst(SMC_PRE(BANK_ADDRESS_R, 0 ,0), SMC_NOP(), SMC_NOP(), SMC_NOP());

p.add_inst(SMC_LI(0, COLUMN_ADDRESS_R));

p.add_inst(SMC_LI(1000,ROW_ADDRESS_R)); // now we do the attack activate agresser row which is 1000 and we started with 999 initialized 3 rows 999 1000 and 1001 1000 is the agressor



const int HAMMER_COUNTER_R = 10;// counter to perform the attack
const int HAMMER_COUNT_R = 11; // the input from the user 

p.add_inst(SMC_LI(hammer_count, HAMMER_COUNT_R)); 
p.add_inst(SMC_LI(0, HAMMER_COUNTER_R));

p.add_label("HAMMER_BEGIN"); // checks to see if condition is satisfied or not 

p.add_inst(SMC_ACT(BANK_ADDRESS_R, 0, ROW_ADDRESS_R, 0), SMC_NOP(), SMC_NOP(), SMC_NOP()); // the row hammer attack is only 4 lines 
p.add_inst(SMC_SLEEP(24));
p.add_inst(SMC_PRE(BANK_ADDRESS_R, 0, 0), SMC_NOP(), SMC_NOP(), SMC_NOP());
p.add_inst(SMC_ADDI(HAMMER_COUNTER_R, 1, HAMMER_COUNTER_R)); //increase hammer counter by 1

p.add_branch(p.BR_TYPE::BL, HAMMER_COUNTER_R, HAMMER_COUNT_R, "HAMMER_BEGIN"); //branch instrcution this function has 4 arguements aka the type of branchcompares hammer counter to hammer count and if hammer counter is lower than hammer count it will jump back to begin

p.add_inst(SMC_LI(999, ROW_ADDRESS_R)); // read from first victim row

const int READ_COUNTER_R = 10;
const int READ_COUNT_R = 11;

p.add_inst(SMC_LI(3, READ_COUNT_R)); // we want to read thre rows
p.add_inst(SMC_LI(0, READ_COUNTER_R));

p.add_label("READ_BEGIN");

p.add_inst(SMC_ACT(BANK_ADDRESS_R, 0, ROW_ADDRESS_R, 0), SMC_NOP(), SMC_NOP(), SMC_NOP());
p.add_inst(SMC_SLEEP(12));
for (int i = 0 ; i < 128 ; i++)
{
    p.add_inst(SMC_READ(BANK_ADDRESS_R, 0, COLUMN_ADDRESS_R, 0, 0, 0), SMC_NOP(), SMC_NOP(), SMC_NOP()); //reads the whole row 
    p.add_inst(SMC_ADDI(COLUMN_ADDRESS_R, 8, COLUMN_ADDRESS_R));
    }
p.add_inst(SMC_SLEEP(5));
p.add_inst(SMC_PRE(BANK_ADDRESS_R,0 ,0), SMC_NOP(), SMC_NOP(), SMC_NOP());

p.add_inst(SMC_LI(0, COLUMN_ADDRESS_R));

// increment row address register by one
p.add_inst(SMC_ADDI(ROW_ADDRESS_R, 1, ROW_ADDRESS_R));
p.add_inst(SMC_ADDI(READ_COUNTER_R, 1, READ_COUNTER_R));

p.add_branch(p.BR_TYPE::BL, READ_COUNTER_R, READ_COUNT_R, "READ_BEGIN"); // does it again same as how we did the read 

p.add_inst(SMC_END()); // lets dram bender know we finished 

platform.execute(p); // executes the program 

p.pretty_print();

unsigned char buf1[8192];

int no_bitflips = 0;

for (int i = 0; i < 3; i++) {
platform.receiveData(buf1, 8192); // One row = 8KiB
char expected_bits = (i % 2 == 0) ? 0xFF : 0x00;

// Printing out the data from the buffer
cout << "Data from buffer (Row " << i << "):" << endl;
for (int j = 0; j < 8192; j++) {
    cout << setw(2) << setfill('0') << hex << static_cast<int>(buf1[j]) << " ";
    if ((j + 1) % 32 == 0) cout << endl;  // Change line every 32 bytes for better readability
}
cout << dec << setfill(' ') << endl;  // Resetting to default formatting

// Checking for bit flips
 for (int j = 0; j < 8192; j++) {
     if (expected_bits != buf1[j]) {  
         no_bitflips += __builtin_popcount(expected_bits ^ buf1[j]);       
     }
 }

}

cout << "Number of bit flips: " << no_bitflips << endl;
platform.reset_fpga();

}

Segmentation Fault Core Dumped

Hello, after following your tutorial on youtube from the video
0:00 / 43:14
P&S DRAM Bender: DRAM Bender Tutorial (Fall 2022)

We are running into an issue where when we run the code for main.cpp we get a Open to card failed! error along with a Segmentation Fault (core dumped)

Downloads/DRAM-Bender-master$ ls
images LICENSE prebuilt projects README.md sources
Downloads/DRAM-Bender-master$ cd sources/
Downloads/DRAM-Bender-master/sources$ cd apps/
Downloads/DRAM-Bender-master/sources/apps$ ls
DebugExample parsertest QUAC-TRNG ResetBoard RetentionTest RowHammerExample SanityCheck Smalltest
Downloads/DRAM-Bender-master/sources/apps$ cd RowHammerExample/
Downloads/DRAM-Bender-master/sources/apps/RowHammerExample$ ls
main.cpp main.o Makefile ps
Downloads/DRAM-Bender-master/sources/apps/RowHammerExample$ ./ps 10
Open to card failed!
Segmentation fault (core dumped)
Downloads/DRAM-Bender-master/sources/apps/RowHammerExample$

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