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cuijialang's Projects

abc icon abc

ABC: System for Sequential Logic Synthesis and Formal Verification

artix-express-35 icon artix-express-35

This is a base design for an Artix-7 35T based FPGA card with PCIE and USB interface. This is meant as an open source, DIY alternative to certain commercial PCIE FPGA development cards.

bar-tender icon bar-tender

An FPGA I/O Device which services physical memory reads/writes via UMDF2 driver

bluespecpcie icon bluespecpcie

PCIe library for the Xilinx 7 series FPGAs in the Bluespec language

corundum icon corundum

Open source FPGA-based NIC and platform for in-network compute

cpcie icon cpcie

CPCIe is a hardware compressor/decompressor implemented on FPGA, to compress/decompress data between Host PC and FPGA via PCIe interface.

dcc icon dcc

Digital signal processing using VHDL, Terasic's DE2i-150 FPGA Development Kit (CPU-FPGA PCIe link) and DCC AD/DA

dcc_adaptable icon dcc_adaptable

Digital signal processing using VHDL and Verilog, Filter coefficients are reloadable during run time via PCIe link. Terasic's DE2i-150 FPGA Development Kit (CPU-FPGA PCIe link) and DCC AD/DA

edalize icon edalize

An abstraction library for interfacing EDA tools

edapack icon edapack

Provides a packaged collection of open source EDA tools

fpga-api icon fpga-api

Capstone Project Spring 2020 demonstrating FPGA data transfers from card to host via PCIe

ghdl icon ghdl

VHDL 2008/93/87 simulator

hdl_antlr4 icon hdl_antlr4

C# projects that use ANTLR4 library to analyse VHDL and Verilog code

hdlconvertor icon hdlconvertor

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTL4

irig-b icon irig-b

IRIG-B HDL implementation and Wishbone interface

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