daglem / redip-cia

MOS 6520 PIA / MOS 6522 VIA / MOS 6526/8520/8521 CIA replacement

reDIP CIA

MOS 6520 PIA / MOS 6522 VIA / MOS 6526/8520/8521 CIA FPGA replacement

Overview

The reDIP CIA is an open source FPGA board which combines the following in a DIP-40 size package:

• Lattice iCE5LP1K FPGA
• 1Mbit FLASH
• 5V tolerant I/O

The reDIP CIA provides an open source hardware platform for MOS 6520 PIA / MOS 6522 VIA / MOS 6526/8520/8521 CIA replacements.

Designs for the iCE5LP1K FPGA can be processed by yosys and nextpnr.

I/O interfaces

DIP-40 header pins:

• 5V input
• 35 FPGA GPIO
• 3 FPGA open-drain I/O
• GND

All FPGA header I/O is 5V tolerant, and can drive 5V TTL.

SPI / programming header:

A separate header footprint is provided for (Q)SPI flash programming, with pinout borrowed from the iCEBreaker Bitsy.

redip-cia's Issues

Question about IO and crystal

Hi Dag. Nice project!
I wonder, I designed a similar board with same fpga as the icebreaker dev board iCE40UP5k, I had trouble figuring out if the RGB IOs are configurable for IO? Maybe it is different for the LP1K. I had trouble getting enough IO for the CIA. Also, will it load the flash without a crystal?
Just wondering. As you may know I made the VHDL6526, tested it with a custom cartridge that I programmed, but never made a PCB for it.
If you have tested this design, I'd like to try myself and use my cartridge to check it.

Hans

Where is the gateware source?

I can only see the pin definitions, but seems that all actual verilog is missing.