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simplenote-ios

Simplenote for iOS

sites

【编程随想】收藏的各色网站

slang

SystemVerilog compiler and language services

sm3_core

solutions

《神经网络与深度学习》课后习题答案-分享讨论

sonnet

TensorFlow-based neural network library

source-code-pro

Monospaced font family for user interface and coding environments

sparse-map

C++ implementation of a memory efficient hash map and hash set

spdlog

Fast C++ logging library.

spdlog-1

Fast C++ logging library.

split-extract

Heterogeneous Feature Extraction for Split Manufactured Layouts with Routing Perturbation

spydrnet

A flexible framework for analyzing and transforming FPGA netlists. Official repository.

ssh-tutorial

SSH 教程

sta

Static Timing Analysis diagram renderer

standard_code_library

Standard_Code_Library

state-of-the-art-shitcode

💩State-of-the-art shitcode principles your project should follow to call it a proper shitcode

static-timing-analysis

Analyzes a boolean circuit together with rising and falling delays, computes valid routes and outputs the best and worst timings for each one.

static-timing-analysis-1

:space_invader: CAD contest 2016 -- Problem D

static-timing-analysis-2

static_timing_analysis

A static timing analysis tool that gets (1) the Verilog gate level net list of a digital circuit, (2) the library of the cells used in the circuit, (3) the net capacitances file, (4) the clocks skew file and (5) timing constraints (the clock period, input delays and output delays). The tool checks all the timing paths and reports the violating timing paths, if any.

std-cell-library-characterization

A repository for my experimental results, and scripts to process, analyze, and interpret them.

surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

sv-parser

SystemVerilog parser library fully complient with IEEE 1800-2017

sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

sv2v

SystemVerilog to Verilog conversion

svf

Static Value-Flow Analysis Framework for Source Code

svlint

SystemVerilog linter

svls

SystemVerilog language server

sw

NVDLA SW

swig

SWIG is a software development tool that connects programs written in C and C++ with a variety of high-level programming languages.